RISC-V Summit has ended

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RISC-V Summit

December 6-8, 2021 | San Fransisco, CA + Virtual
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7:00am PST

Registration + Vaccine Verification Level 1 Foyer

9:00am PST

A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India Room 3005/3007 XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS) Room 3004/3006

9:30am PST

Lightning Talk: Improving Performance of National Crypto Algorithms with Custom Instructions - Alexander Kozlov, CloudBEAR Room 3004/3006 Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications - Shubu Mukherjee, SiFive Room 3005/3007

9:45am PST

Lightning Talk: A System Level Verification and Validation Environment using SweRV - Anupam Bakshi, Agnisys, Inc. Room 3004/3006

10:00am PST

Break TBA Expo Hall Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:05am PST

Demo: RISC-V Successful Stories of Andes Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:20am PST

Demo: Introducing the PolarFire® SoC Smart Embedded Vision Kit - Avery Williams, Microchip Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:30am PST

Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar, TU Dresden & Dr. William Jones, Embecosm Room 3004/3006 Open Hardware for the Open Cloud - Daniel Mangum, Upbound Room 3005/3007

10:45am PST

Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software Room 3004/3006

11:00am PST

Lightning Talk: De-RISC, the Horizon 2020 Project that will Create the First RISC-V, Fully European Platform for Aerospace - Paco Gómez-Molinero, fentISS Room 3004/3006 Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services Room 3005/3007

11:15am PST

Lightning Talk: Adding 32-bit Linux Support to ARIANE/CVA6 Open-source Application Core - Sébastien Jacq & Jérôme Quévremont, Thales Room 3004/3006

11:30am PST

Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC Room 3005/3007 Extending RISC-V Instructions for 5G Intelligent RAN Base Stations - Gururaj Padaki & Sriram Rajagopal, EdgeQ Room 3004/3006

12:00pm PST

Lunch Break (Attendees on Own) TBA

1:30pm PST

Keynote: Welcome & Opening Remarks - Calista Redmond, CEO, RISC-V International Room 3008 - 3012

1:40pm PST

Keynote: Are the RISC-V Design Freedoms Leading to RISK in Verification Quality? - Larry Lapides, Vice President Sales, Imperas Software Ltd. Room 3008 - 3012

1:55pm PST

Keynote: Bringing RISC-V to Life: Building our Software Ecosystem - Philipp Tomsich, Founder and Chief Technologist, VRULL GmbH Room 3008 - 3012

2:10pm PST

Keynote: The Future of RISC-V has No Limits - Dr. Yunsup Lee, Co-Founder & Chief Technology Officer, SiFIve Room 3008 - 3012

2:30pm PST

Keynote: The Showcase of RISC-V Wins! Room 3008 - 3012

2:35pm PST

Keynote: Building Customized Solutions from Open-sources - Xiaoning Qi, Vice President, Alibaba Group Room 3008 - 3012

2:45pm PST

Keynote: Diversity, Equity, and Inclusion in Open Hardware - Dr. Marjan Radi, Research Technologist Engineer, NVM Systems Architecture, Western Digital & Kim McMahon, Director of Visibility & Community Engagement... Room 3008 - 3012

3:00pm PST

Break TBA

3:05pm PST

Demo: 10 Minute RISC-V Custom Instructions - Zdenek Přikryl, Codasip Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:20pm PST

Demo: Containers and Kubernetes in the RISC-V Architecture - Carlos Eduardo de Paula, Red Hat Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:30pm PST

YoC, an Open Operation System for IoT - Vincent Cui, Alibaba Room 3005/3007 RISC-V on Edge: Porting EVE and Alpine Linux to RISC-V - Roman Shaposhnik & Kathy Giori, ZEDEDA Inc. Room 3004/3006

4:00pm PST

Lightning Talk: Accelerating Real-World AI Software using the RISC-V Vector Extension - Colin Davidson & Alastair Murray, Codeplay Software Room 3004/3006 Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA Room 3005/3007

4:15pm PST

Lightning Talk: Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks - David Luo, Mythic & Dr Zdeněk Přikryl, Codasip Room 3004/3006

4:30pm PST

Advanced Interrupt Architecture and Advanced CLINT - Anup Patel, Western Digital & John Hauser, Independent Researcher Room 3005/3007 Hard Real-Time vs High Performance Real-Time Applications on PolarFire SoC - Hugh Breslin, Microchip Technology Room 3004/3006

4:55pm PST

Break TBA

5:05pm PST

Demo: Hands-on with SiFive Performance P550 and SiFive Freedom Studio - Joshua Smith, SiFive Exhibit Hall - 2nd Floor - RISC-V Demo Theater

5:30pm PST

Scavenger Hunt Prize Drawing Exhibit Hall - 2nd Floor - RISC-V Demo Theater

8:00am PST

Registration + Vaccine Verification Level 1 Foyer

9:00am PST

Support for Non-Coherent I/O Devices in RISC-V - Greg Favor & David Kruckemyer, Ventana Micro Systems Room 3005/3007 Performance Monitoring in RISC-V using perf - Atish Patra, Western Digital Room 3004/3006

9:30am PST

Continuous Innovation in Embedded RISC-V Processors - Drew Barbier, SiFive Room 3005/3007 ACPI for RISC-V: Enabling Server Class Platforms - Sunil V L, Ventana Micro Systems Room 3004/3006

10:00am PST

Break TBA Expo Hall Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:05am PST

Demo: Formal Verification of RISC-V Cores - Saša Stamenković, OneSpin Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:20am PST

Demo: Brief Introduction to the 5 Levels of RISC-V Processor Verification - Kevin McDermott & Lee Moore, Imperas Software Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:30am PST

Efficient Issue Scheduling for Hardware Multithreaded RISC-V Pipeline - Dr. Shlomo Greenberg, Ben Gurion University of the Negev & Sami Shamoon College Engineering, Beer-Sheva, Israel Room 3004/3006 RISC-V Compatible Processor IP by Syntacore: Compact Open-source MCU to Multicore Linux - John Hartley, Syntacore Room 3005/3007

11:00am PST

Lightning Talk: RISQV-HT: A RISC-V Microcontroller Delivering Post-Quantum Secure Encryption - and Hardware Trojans - Alexander Hepp, Technical University of Munich Room 3005/3007 The Future of RISC-V Heterogeneous Embedded Virtualization Architectures - Sandro Pinto & José Martins, Universidade do Minho Room 3004/3006

11:15am PST

Lightning Talk: Enabling Software Emulation for RISC-V Heterogeneous Cores Architecture - Cui Jin & Ley Foon Tan, StarFive Technology Room 3005/3007

11:30am PST

Accelerating AI and non-AI Workloads with 1000+ Energy-Efficient RISC-V Cores on a Single Chip - Art Swift, Esperanto Technologies Room 3004/3006 RISC-V Debug in the OS-A Platform - Paul Donahue, Ventana Micro Systems Room 3005/3007

12:00pm PST

Lunch Break (Attendees on Own) TBA

1:30pm PST

Keynote: State of the Union - Krste Asanović, Professor, EECS Dept, U.C Berkeley / Chief Architect and Co-Founder, SiFive Inc. Room 3008 - 3012

1:45pm PST

Keynote: Beefing Up the Datacenter Accelerators - Charlie Su, President and CTO, Andes Technology Room 3008 - 3012

1:55pm PST

Keynote Panel: RISC-V Momentum at Data Center Scale - Balaji Baktha, Ventana (Moderator); Sumit Gupta, Google; Jing Yang, Alibaba; Roger Espasa, Semidynamics Technology Services; Bapi Vinnakota, Open Compute Project... Room 3008 - 3012

2:25pm PST

Keynote: Microchip and the Expanding RISC-V Universe - Ted Speers, Technical Fellow, Microchip Room 3008 - 3012

2:35pm PST

Keynote: The Showcase of RISC-V Wins! Room 3008 - 3012

2:40pm PST

Keynote: Profiles and Platforms: RISC-V Convergence - Greg Favor, CTO, Ventana Micro Systems Room 3008 - 3012

3:00pm PST

Break TBA

3:05pm PST

Demo: Hands-on with SiFive Performance P550 and SiFive Freedom Studio - John Ingalls, SiFive Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:20pm PST

Demo: How Software can Enable your Next RISC-V Device - Jeff Hancock, Siemens Embedded Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:30pm PST

AI-RISC - Custom Extensions to RISC-V for Energy-efficient AI Inference at the Edge of IoT - Vaibhav Verma, University of Virginia Room 3005/3007 Sail Specification for RISC-V P-Extension - Bow-Yaw Wang, Academia Sinica, Taiwan & Jenq-Kuen Lee, National Tsing Hua University, Taiwan Room 3004/3006

4:00pm PST

Exploring the Zce Code-size Reduction ISA Extension - Tariq Kurd, Huawei UK Room 3005/3007 BoF: How RISC-V CPU Design Impacts Performance of Copy Function and Network Speed - Akira Tsukamoto, AIST Room 3004/3006

4:30pm PST

Webassembly as Managed Runtime VM in Embedded Systems - Stefan Wallentowitz, Munich University of Applied Sciences Room 3005/3007

4:55pm PST

Break

5:30pm PST

Scavenger Hunt Prize Drawing Exhibit Hall - 2nd Floor - RISC-V Demo Theater

8:00am PST

Registration + Vaccine Verification Level 1 Foyer

9:00am PST

Lightning Talk: Functional Gap between RISC-V V and SPIR-V: a Study Case on the Graphics Domain - Abel Bernabeu, Esperanto Technologies Room 3005/3007 RISC-V Enterprise Software Ecosystem Readiness - Kumar Sankaran, Ventana Micro Systems Room 3004/3006

9:15am PST

Lightning Talk: A Zero Trust Security Architecture For RISC-V SoC/ Platform - Suresh Sugumar, Technology Innovation Institute Room 3005/3007

9:30am PST

Esperanto’s Custom RISC-V ISA Extensions for Energy-Efficient Machine Learning Applications - Jayesh Iyer, Esperanto Technologies Room 3004/3006 Radiation Hardening and Fault-Tolerance Features of the NOEL-V RISC-V Processor - Jan Andersson, CAES Space System Division, Gaisler Room 3005/3007

10:00am PST

Break TBA Expo Hall Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:05am PST

Demo: RISC-V Software Debug in an Emulation Environment - Andy Meier, Siemens Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:20am PST

Demo: Software Design: Porting Software to RISC-V using Imperas Virtual Platforms - Katherine (Kat) Hsu & Manny Wright, Imperas Software Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:30am PST

Lightning Talk: Adding H Support to the NOEL-V Microprocessor - Stefano Ribes, De-RISC Project Room 3005/3007 Quantitative Methods for Continuously Improving RISC-V Compilers - Philipp Tomsich, VRULL Room 3004/3006

10:45am PST

Lightning Talk: A Secure RISC-V Based SoC for Autonomous UAVs Navigation - Davide Rossi, University of Bologna & Daniele Palossi, IDSIA USI-SUPSI Lugano Room 3005/3007

11:00am PST

Lightning Talk: Performance of TVM AutoScheduler for Andes Vector Processor - I-Wei Wu, Andes Technology Room 3004/3006 Unveiling the SweRV Core EH3 - Zvonimir Bandic, Western Digital Room 3005/3007

11:15am PST

Lightning Talk: Bring Multicore RISC-V and Zephyr RTOS Together - Chun-Wei Shu, Andes Technology Room 3004/3006

11:30am PST

Profiles and Platforms - Philipp Tomsich, VRULL & Mark Himelstein, RISC-V International Room 3005/3007 A Requirements-based Test Suite for the C Standard Library: SuperGuard - Marcel Beemster, Solid Sands B.V. Room 3004/3006

12:00pm PST

Lunch Break (Attendees on Own) TBA

1:30pm PST

Keynote: Road Ahead - Mark Himelstein, CTO, RISC-V International Room 3008 - 3012

1:50pm PST

Keynote: Is Hardware/software Co-design for Applications Now a Reality with RISC-V? - Kevin McDermott, Vice President Marketing, Imperas Software Ltd Room 3008 - 3012

2:00pm PST

Keynote: Awards Presentation - Kim McMahon, Director of Visibility & Community Engagement, RISC-V International & Mark Himelstein, CTO, RISC-V International Room 3008 - 3012

2:15pm PST

Keynote: Scaling is Failing - Dr. Ron Black, CEO, Codasip Room 3008 - 3012

2:30pm PST

Keynote: The Showcase of RISC-V Wins! Room 3008 - 3012

2:40pm PST

Keynote: Where is RISC-V Going? - Calista Redmond, CEO, RISC-V International Room 3008 - 3012

3:00pm PST

Break TBA

3:05pm PST

Demo: Processor Trace: Efficient Solutions for Today’s SoCs - Hanan Moller, Siemens EDA Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:20pm PST

Demo: Debian Linux at octacore SCR7-based SDK - Sergey Yakushkin, Syntacore Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:30pm PST

Systematically Securing the RISCV - Secure Foundation for Embedded Functionality - Marko Mitic, NVIDIA Room 3005/3007 TEEP (Trusted Execution Environment Provisioning) and Software Updates for Internet of Things (SUIT) on RISC-V - Akira Tsukamoto, AIST Room 3004/3006

4:00pm PST

Lightning Talk: Enabling RISC-V Software Ecosystem with VisionFive - an Affordable and Open Source RISC-V Single Board Development Platform with Support for Fedora - Chin Hu Ong, StarFive Technology Room 3004/3006 IOPMP Updates: The Protection of IOPMP - Paul Shan-Chyun Ku, Andes Technology Room 3005/3007

4:15pm PST

Lightning Talk: First Volume Production RISC-V Silicon/SOC to Provide Complete Personal Computing Platform Solution Targeting Mid-range and Edge Computing - Johnson Sun, StarFive Room 3004/3006

4:30pm PST

Architecture Design for Security: Do’s and Don’ts - Gregory T. Sullivan, Dover Microsystems, Inc. Room 3005/3007 Storage Area Network Acceleration using RDMA / RoCE and RISC-V - Pu Wang, DatenLord Room 3004/3006

4:55pm PST

Break TBA

5:30pm PST

Scavenger Hunt Prize Drawing Exhibit Hall - 2nd Floor - RISC-V Demo Theater