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9:00am • XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)
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9:30am • Lightning Talk: Improving Performance of National Crypto Algorithms with Custom Instructions - Alexander Kozlov, CloudBEAR
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9:45am • Lightning Talk: A System Level Verification and Validation Environment using SweRV - Anupam Bakshi, Agnisys, Inc.
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10:30am • Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar, TU Dresden & Dr. William Jones, Embecosm
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10:45am • Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software
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11:00am • Lightning Talk: De-RISC, the Horizon 2020 Project that will Create the First RISC-V, Fully European Platform for Aerospace - Paco Gómez-Molinero, fentISS
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11:15am • Lightning Talk: Adding 32-bit Linux Support to ARIANE/CVA6 Open-source Application Core - Sébastien Jacq & Jérôme Quévremont, Thales
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11:30am • Extending RISC-V Instructions for 5G Intelligent RAN Base Stations - Gururaj Padaki & Sriram Rajagopal, EdgeQ
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3:30pm • RISC-V on Edge: Porting EVE and Alpine Linux to RISC-V - Roman Shaposhnik & Kathy Giori, ZEDEDA Inc.
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4:00pm • Lightning Talk: Accelerating Real-World AI Software using the RISC-V Vector Extension - Colin Davidson & Alastair Murray, Codeplay Software
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4:15pm • Lightning Talk: Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks - David Luo, Mythic & Dr Zdeněk Přikryl, Codasip
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4:30pm • Hard Real-Time vs High Performance Real-Time Applications on PolarFire SoC - Hugh Breslin, Microchip Technology
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9:00am • A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India
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9:30am • Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications - Shubu Mukherjee, SiFive
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10:30am • Open Hardware for the Open Cloud - Daniel Mangum, Upbound
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11:00am • Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services
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11:30am • Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC
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3:30pm • YoC, an Open Operation System for IoT - Vincent Cui, Alibaba
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4:00pm • Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA
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4:30pm • Advanced Interrupt Architecture and Advanced CLINT - Anup Patel, Western Digital & John Hauser, Independent Researcher
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1:30pm • Keynote: Welcome & Opening Remarks - Calista Redmond, CEO, RISC-V International
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1:40pm • Keynote: Are the RISC-V Design Freedoms Leading to RISK in Verification Quality? - Larry Lapides, Vice President Sales, Imperas Software Ltd.
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1:55pm • Keynote: Bringing RISC-V to Life: Building our Software Ecosystem - Philipp Tomsich, Founder and Chief Technologist, VRULL GmbH
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2:10pm • Keynote: The Future of RISC-V has No Limits - Dr. Yunsup Lee, Co-Founder & Chief Technology Officer, SiFIve
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2:30pm • Keynote: The Showcase of RISC-V Wins!
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2:35pm • Keynote: Building Customized Solutions from Open-sources - Xiaoning Qi, Vice President, Alibaba Group
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2:45pm • Keynote: Diversity, Equity, and Inclusion in Open Hardware - Dr. Marjan Radi, Research Technologist Engineer, NVM Systems Architecture, Western Digital & Kim McMahon, Director of Visibility & Community Engagement, RISC-V International
