RISC-V Summit has ended

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RISC-V Summit

December 6-8, 2021 | San Fransisco, CA + Virtual
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9:00am PST

A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India Room 3005/3007 XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS) Room 3004/3006

9:30am PST

Lightning Talk: Improving Performance of National Crypto Algorithms with Custom Instructions - Alexander Kozlov, CloudBEAR Room 3004/3006

10:05am PST

Demo: RISC-V Successful Stories of Andes Exhibit Hall - 2nd Floor - RISC-V Demo Theater

10:30am PST

Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar, TU Dresden & Dr. William Jones, Embecosm Room 3004/3006

10:45am PST

Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software Room 3004/3006

11:00am PST

Lightning Talk: De-RISC, the Horizon 2020 Project that will Create the First RISC-V, Fully European Platform for Aerospace - Paco Gómez-Molinero, fentISS Room 3004/3006

11:30am PST

Extending RISC-V Instructions for 5G Intelligent RAN Base Stations - Gururaj Padaki & Sriram Rajagopal, EdgeQ Room 3004/3006

3:20pm PST

Demo: Containers and Kubernetes in the RISC-V Architecture - Carlos Eduardo de Paula, Red Hat Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:30pm PST

YoC, an Open Operation System for IoT - Vincent Cui, Alibaba Room 3005/3007 RISC-V on Edge: Porting EVE and Alpine Linux to RISC-V - Roman Shaposhnik & Kathy Giori, ZEDEDA Inc. Room 3004/3006

4:00pm PST

Lightning Talk: Accelerating Real-World AI Software using the RISC-V Vector Extension - Colin Davidson & Alastair Murray, Codeplay Software Room 3004/3006

4:30pm PST

Advanced Interrupt Architecture and Advanced CLINT - Anup Patel, Western Digital & John Hauser, Independent Researcher Room 3005/3007 Hard Real-Time vs High Performance Real-Time Applications on PolarFire SoC - Hugh Breslin, Microchip Technology Room 3004/3006

9:00am PST

Performance Monitoring in RISC-V using perf - Atish Patra, Western Digital Room 3004/3006

9:30am PST

ACPI for RISC-V: Enabling Server Class Platforms - Sunil V L, Ventana Micro Systems Room 3004/3006

10:30am PST

Efficient Issue Scheduling for Hardware Multithreaded RISC-V Pipeline - Dr. Shlomo Greenberg, Ben Gurion University of the Negev & Sami Shamoon College Engineering, Beer-Sheva, Israel Room 3004/3006

11:15am PST

Lightning Talk: Enabling Software Emulation for RISC-V Heterogeneous Cores Architecture - Cui Jin & Ley Foon Tan, StarFive Technology Room 3005/3007

3:20pm PST

Demo: How Software can Enable your Next RISC-V Device - Jeff Hancock, Siemens Embedded Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:30pm PST

Sail Specification for RISC-V P-Extension - Bow-Yaw Wang, Academia Sinica, Taiwan & Jenq-Kuen Lee, National Tsing Hua University, Taiwan Room 3004/3006

4:00pm PST

Exploring the Zce Code-size Reduction ISA Extension - Tariq Kurd, Huawei UK Room 3005/3007 BoF: How RISC-V CPU Design Impacts Performance of Copy Function and Network Speed - Akira Tsukamoto, AIST Room 3004/3006

4:30pm PST

Webassembly as Managed Runtime VM in Embedded Systems - Stefan Wallentowitz, Munich University of Applied Sciences Room 3005/3007

9:15am PST

Lightning Talk: A Zero Trust Security Architecture For RISC-V SoC/ Platform - Suresh Sugumar, Technology Innovation Institute Room 3005/3007

9:30am PST

Radiation Hardening and Fault-Tolerance Features of the NOEL-V RISC-V Processor - Jan Andersson, CAES Space System Division, Gaisler Room 3005/3007

10:30am PST

Lightning Talk: Adding H Support to the NOEL-V Microprocessor - Stefano Ribes, De-RISC Project Room 3005/3007

10:45am PST

Lightning Talk: A Secure RISC-V Based SoC for Autonomous UAVs Navigation - Davide Rossi, University of Bologna & Daniele Palossi, IDSIA USI-SUPSI Lugano Room 3005/3007

11:00am PST

Lightning Talk: Performance of TVM AutoScheduler for Andes Vector Processor - I-Wei Wu, Andes Technology Room 3004/3006

11:15am PST

Lightning Talk: Bring Multicore RISC-V and Zephyr RTOS Together - Chun-Wei Shu, Andes Technology Room 3004/3006

11:30am PST

A Requirements-based Test Suite for the C Standard Library: SuperGuard - Marcel Beemster, Solid Sands B.V. Room 3004/3006

3:20pm PST

Demo: Debian Linux at octacore SCR7-based SDK - Sergey Yakushkin, Syntacore Exhibit Hall - 2nd Floor - RISC-V Demo Theater

3:30pm PST

TEEP (Trusted Execution Environment Provisioning) and Software Updates for Internet of Things (SUIT) on RISC-V - Akira Tsukamoto, AIST Room 3004/3006

4:00pm PST

Lightning Talk: Enabling RISC-V Software Ecosystem with VisionFive - an Affordable and Open Source RISC-V Single Board Development Platform with Support for Fedora - Chin Hu Ong, StarFive Technology Room 3004/3006 IOPMP Updates: The Protection of IOPMP - Paul Shan-Chyun Ku, Andes Technology Room 3005/3007

4:15pm PST

Lightning Talk: First Volume Production RISC-V Silicon/SOC to Provide Complete Personal Computing Platform Solution Targeting Mid-range and Edge Computing - Johnson Sun, StarFive Room 3004/3006

4:30pm PST

Architecture Design for Security: Do’s and Don’ts - Gregory T. Sullivan, Dover Microsystems, Inc. Room 3005/3007 Storage Area Network Acceleration using RDMA / RoCE and RISC-V - Pu Wang, DatenLord Room 3004/3006