RISC-V Summit

The existing RISC-V platforms only support wired interrupts, machine-level timer interrupts and machine-level software interrupts in hardware hence there is no hardware support for message signaled interrupts (MSIs), MSI virtualization, and supervisor-level software interrupts. The advanced interrupt architecture (AIA) specification defines new interrupt controllers to support wired interrupts, MSIs and MSI virtualization in manner scalable for large number of HARTs. The advanced core local interruptor (ACLINT) specification defines separate devices for machine-level timer interrupts, machine-level software interrupts, and supervisor-level software interrupts in a manner backward-compatible for existing RISC-V platforms. The AIA and ACLINT specifications collectively address interrupt and timer requirements of different classes of RISC-V platforms.