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December 6-8, 2021 | San Fransisco, CA + Virtual
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Tuesday, December 7 • 4:00pm - 4:25pm
Exploring the Zce Code-size Reduction ISA Extension - Tariq Kurd, Huawei UK

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Tariq, the chair of code-size reduction TG, will give an overview of the new Zce extension , explaining the new instructions and showing how they help reduce code size for a wide range of applications. Benchmarking work is seesentionf or the design of Zce. Ibrahim will explain how it was done and will demonstrate how to benchmark your own applications using his analysis script.

Speakers
TK

Tariq Kurd

CPU Architect, Huawei UK
I have over 20 years of CPU archiecture, design and verification, mainly in the embedded space. I've worked on VLIW, multi-threaded, out-of-order cores, security and DSP style cores. I've been at Huawei for 6+ years, and previously was at Broadcom and Nvidia. I'm the chair of the... Read More →



Tuesday December 7, 2021 4:00pm - 4:25pm PST
Room 3005/3007
  Beyond the RISC-V ISA
  • Talk Type Virtual
  • Presentation Slides Attached Yes