RISC-V Summit

RISC-V P-extension (RVP) is designed for digital signal processing (DSP) applications on RISC-V instruction set architecture. RVP supports parallel processing with 325 new instructions. Among them, 173 Single-Instruction-Multiple-Data (SIMD) instructions are added. These instructions divide general purposed registers into 8-, 16-, 32-, or 64-bit chunks and compute an arithmetic function in parallel. RVP also contains special instructions for DSP such as cross multiplication and saturated computation. The RVP specification is a text document maintained by the RVP work group. We present a Sail specification for RVP in this work. To reduce manual and maintenance efforts, tedious Sail specifications for binary encoder/decoder and assembly mnemonics are generated automatically. We explain how dependent-type programming in Sail simplifies our semantic functions for RVP. Writing semantic functions for 325 instructions in RVP is still tedious and prone to errors. Inconsistency between the textual RVP specification and our Sail specification can be embarrassing. Using Spike, we present a workflow to validate our Sail specification for the 325 instructions defined in RVP.