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December 6-8, 2021 | San Fransisco, CA + Virtual
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Monday, December 6 • 11:00am - 11:25am
Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services

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In this talk we will describe Semidynamics' vector unit implementing the RVV-010 specification and we will focus on the challenges of supporting out-of-order execution for vector instructions. We will cover the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. We will also provide an overview of the vector load/store pipeline.

avatar for Roger Espasa

Roger Espasa

CEO, Semidynamics Technology Services SLU
Roger Espasa got his Phd in Computer Science from Universitat Politècnica de Catalunya in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Between 2002 and 2014 Roger worked at Intel developing... Read More →

Monday December 6, 2021 11:00am - 11:25am PST
Room 3005/3007
  Beyond the RISC-V ISA