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December 6-8, 2021 | San Fransisco, CA + Virtual
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Wednesday, December 8 • 4:00pm - 4:25pm
IOPMP Updates: The Protection of IOPMP - Paul Shan-Chyun Ku, Andes Technology

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Platform security is an investable issue nowadays. One fundamental requirement is memory isolation. Inside a RISC-V core, PMP creates isolated spaces. In a platform, IOPMPs do it for the other bus masters. However, the system becomes vulnerable if the malicious code manipulates an IOPMP and allows illegal access. Thus, IOPMPs should also be protected. Unlike PMP, IOPMP has no corresponding CSRs whose access right is constraint by processor modes. IOPMP should recognize the legal control operations first, that is, those accesses from the security monitor. Furthermore, IOPMPs should be able to protect some sensitive data even when the security monitor is breached. A dedicated IOPMP can be used to bridge the MMIO bus and all bus masters, and at the same time to block out illegal control operations to the rest of IOPMPs as well as itself as a way of protection. Such a way controls the operations in a grain of as fine as 4 bytes. When we only want to lock several bits in a control register, e.g., enforce a certain source id to associate with a specific memory domain, we need a fine-grained lock mechanism. In this talk, we will also present these approaches to protect IOPMPs.

avatar for Paul Shan-Chyun Ku

Paul Shan-Chyun Ku

Deputy Technical Director, Andes Technology
Dr. Ku is working for Andes Technology Corporation and is enthusiastic about processor and platform security. Besides, in RISC-V International Association, he serves the TEE Task Group as the vice-chair and is currently focusing on the IOPMP proposal. He ever worked for Faraday Technology... Read More →

Wednesday December 8, 2021 4:00pm - 4:25pm PST
Room 3005/3007
  Beyond the RISC-V ISA
  • Talk Type Virtual
  • Presentation Slides Attached Yes