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Tuesday, December 7 • 9:00am - 9:25am
Support for Non-Coherent I/O Devices in RISC-V - Greg Favor & David Kruckemyer, Ventana Micro Systems

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The current RISC-V ISA privilege specification only defines a broad physical memory attribute (PMA) mechanism to implement non-cacheable memory regions for any non-coherent I/O devices. While this is an acceptable approach in an embedded world, it is not sufficient for modern-day systems where the number of programmable PMAs will not scale. On other hand, having a fully coherent system is not always feasible due to design costs in spite of performance advantages. Thus, any platform with non- coherent I/O devices relies on the software managed coherency, a widely adopted approach in today's industry. The software can manage coherency either by accessing the memory in such a way that it is never cached or use cache maintenance instructions for cacheable memory. The Svpbmt(Page Based Memory Type) extension was recently proposed to provide a solution to the first approach while a set of CMO(Zicbom, Zicboz, and Zicbop) extensions are the solution to the second approach. These proposed extensions allow the platform vendors to build cost-effective RISC-V systems that are truly on par with other ISAs. This talk will outline the technical details and current status of both extensions.

avatar for Greg Favor

Greg Favor

CDO, Ventana Micro Systems
Greg has been architecting and designing microprocessors for 38 years, both at startups and large companies, and across many architectures including x86, PowerPC, ARMv8, and now RISC-V. Most recently this includes being co-founder and CTO of Ventana Micro Systems, which is developing... Read More →
avatar for David Kruckemyer

David Kruckemyer

Principal Engineer, Ventana Micro Systems, Inc.
David is a Principal Engineer and System Architect at Ventana Micro Systems, leading the development of the RISC-V-based processor cluster and chiplet architecture for the company's products. Outside of Ventana, he is currently active in multiple RISC-V task groups, and he previously... Read More →

Tuesday December 7, 2021 9:00am - 9:25am PST
Room 3005/3007
  Beyond the RISC-V ISA