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December 6-8, 2021 | San Fransisco, CA + Virtual
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Wednesday, December 8 • 9:30am - 9:55am
Radiation Hardening and Fault-Tolerance Features of the NOEL-V RISC-V Processor - Jan Andersson, CAES Space System Division, Gaisler

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NOEL-V is a is a RISC-V processor model that can be implemented in various configurations ranging from RV32I to RCV64GC. The NOEL-V processor has been developed by the CAES Gaisler Products group that has a long heritage of supplying processor implementations, both as IP cores and as ready-made radiation-tolerant standard products, for space applications. Jan Andersson will provide an overview of the fault-tolerance features implemented in the NOEL-V processor core and a description of the first radiation-hardened testchip. The presentation will describe how hardening measures against radiation effects is tied to different target technologies (for example ASIC vs. FPGA) and will also provide an overview of the GR7xV development, which is a 16-core RISC-V based processor targeted towards space applications.

avatar for Jan Andersson

Jan Andersson

Director, Engineering, Cobham Gaisler AB
Mr Jan Andersson M.Sc in Computer Engineering focused on digital design and embedded systems. Working for CAES as Director of Engineering for Gaisler Products, where he oversees hardware and software development efforts and leads implementation of the system-on-chip architecture roadmap... Read More →

Wednesday December 8, 2021 9:30am - 9:55am PST
Room 3005/3007
  Beyond the RISC-V ISA
  • Talk Type Virtual
  • Presentation Slides Attached Yes