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December 6-8, 2021 | San Fransisco, CA + Virtual
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Monday, December 6 • 11:30am - 11:55am
Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC

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The availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores. This talk presents Vitruvius, the first RISC-V vector accelerator developed at BSC for the Supercomputing domain. Vitruvius is compliant with the RISC-V vector extension specification V0.7.1. and can be easily connected to a scalar core using the Open Vector Interface (OVI) standard in a plug-and-play fashion. Vitruvius natively supports long vectors: 256 Double Precision (DP) floating-point elements in a single vector instruction. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File (VRF) and functional units (one integer, one floating-point). It adopts a novel hybrid in-order/out-of-order execution scheme, supported by vector register renaming and arithmetic/memory instruction decoupling. When configured with eight vector lanes, Vitruvius reaches a maximum frequency of 1.25 GHz when synthesized using GLOBALFOUNDRIES 22FDX FD-SOI. The silicon implementation has a total area of 1.13 mm2 and total estimated power of 1648 mW.

Speakers
avatar for Francesco Minervini

Francesco Minervini

Research Engineer, Barcelona Supercomputing Center - BSC
Francesco Minervini received the MSc. and the BSc. from the University of Rome "La Sapienza" in 2018 and 2015, respectively. He has been working as an RTL Research Engineer for BSC for three years, as the main designer of the EPI (European Processor Initiative) Vector Accelerator... Read More →
OP

Oscar Palomar Perez

Established Researcher, Barcelona Supercomputing Center - BSC
Oscar Palomar received a B.S. in Computer Science and PhD degree on Computer Architecture from the Polytechnic University of Catalonia (UPC), Spain. He joined the Computer Architecture for Parallel Paradigms research group at the Barcelona Supercomputing Center as a post-doc. There... Read More →



Monday December 6, 2021 11:30am - 11:55am PST
Room 3005/3007
  Beyond the RISC-V ISA