RISC-V Summit

The world market for aerospace computing systems faces a significant shift caused by the loss of momentum of the traditionally used instruction set architectures in the commercial domain. RISC-V offers a unique opportunity to develop EU-based products for the aerospace domain with no dependence on non-European technology or proprietary IP rights, which would impose licensing fees and export restrictions otherwise. De-RISC project brings together leading European entities within the areas of fault-tolerant microprocessors, hypervisors, embedded safety-critical software and mixed-criticality systems in an effort to commercialize a complete technology stack. The goal is to create a multicore platform for the aerospace industry based on the open RISC-V instruction set architecture together with specific features to address the needs of the target industries and to adopt modern commercial technology leveraging technology developments for other domains. This session covers concepts related to hardware Systems-on-Chip, XtratuM hypervisor, space qualification, and use cases for RISC-V based systems supporting high integrity levels, mixed-criticality, high performance, and dependability.