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December 6-8, 2021 | San Fransisco, CA + Virtual
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Tuesday, December 7 • 4:00pm - 4:55pm
BoF: How RISC-V CPU Design Impacts Performance of Copy Function and Network Speed - Akira Tsukamoto, AIST

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(*) What do these kernel patches do for communication networks? (*) Why the performance improves compared to historical copy function (*) The way to optimize software from the book, Computer Architecture: A Quantitative Approach on RISC-V (*) Why the CPU design impacts implementation of software The patches to improve the performance of RISC-V were accepted on June 4th at the Linux Kernel Mailing List. The changes were achieved by optimizing copy functions inside the kernel by mainly reducing the misaligned memory access and pipeline stalls. The knowledge and understanding of the internals of the RISC-V is essential for optimizing hardware level software. The discussion of the optimization took place in the mailing list and forum of RISC-V development board. The RISC-V is the perfect combination of open architecture and open collaboration to improve the industry since it is open ISA and anybody could participate in the public discussions. The talk will also cover how the Computer Architecture knowledge helps to track down the reason and details of improvement in functions of __asm_copy_from-to_user.

Speakers
avatar for Akira Tsukamoto

Akira Tsukamoto

Senior Researcher, AIST (The National Institute of Advanced Industrial Science and Technology Japan)
Akira Tsukamoto works at AIST (The National Institute of Advanced Industrial Science and Technology Japan). His main focusing area is on both software engineering and hardware engineering on network, operating system and system security. He is enthusiastic on any kind of technical... Read More →



Tuesday December 7, 2021 4:00pm - 4:55pm PST
Room 3004/3006
  Software Stack Integration and Development Tools
  • Talk Type Virtual
  • Presentation Slides Attached Yes