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December 6-8, 2021 | San Fransisco, CA + Virtual
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Monday, December 6 • 11:15am - 11:25am
Lightning Talk: Adding 32-bit Linux Support to ARIANE/CVA6 Open-source Application Core - Sébastien Jacq & Jérôme Quévremont, Thales

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Together with OpenHW, Thales runs the CVA6 project, to transform ETH Zürich and University of Bologna’s ARIANE famous RISC-V application core into an industrial-grade core available as open-source for the community. From the original 64-bit ARIANE SystemVerilog design, renamed CV64A6 by OpenHW, Thales has created a 32-bit flavor, CV32A6, a resource-optimized version for embedded applications that need to support rich OSes like Linux. CV64A6 and CV32A6 share the same code base “CVA6”. In this talk, members of the CVA6 team will present the journey towards the support of Linux by CV32A6: designing a new 32-bit (Sv32) MMU, debugging the 32-bit pipeline, integrating a bootloader and Linux kernel with Buildroot, running a HW/SW integration and debugging and finally demonstrating a running Linux on a FPGA board. As a takeaway, the audience will be pointed to the open-source repositories that they can use to implement CVA6 and Linux when they return home. The next steps in this open-source project are the optimization of CV32A6 to target FPGA platforms (in addition to ASIC technologies), the addition of a few safe&secure features, more verification to get an industrial-grade IP…

avatar for Jérôme Quévremont

Jérôme Quévremont

RISC-V and open hardware project leader, Thales
Jérôme Quévremont is RISC-V and open hardware project leader at Thales Research and Technology (TRT), Palaiseau, France. He serves as the chair of the OpenHW Group Technical WG and the technical leader of the CVA6 (formerly ARIANE) application core project. He is also the chairman... Read More →
avatar for Sébastien Jacq

Sébastien Jacq

Research engineer, Thales
Sébastien Jacq is research engineer at Thales Research and Technology. He specializes in the design of digital computational architecture and in the implementation of algorithms on FPGA / SoC / MPSoC target. Sébastien is currently an actor in the RISC-V community. He actively contributes... Read More →

Monday December 6, 2021 11:15am - 11:25am PST
Room 3004/3006
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