Loading…
Attending this event?
December 6-8, 2021 | San Fransisco, CA + Virtual
Learn More & Register Now

Back To Schedule
Monday, December 6 • 4:15pm - 4:25pm
Lightning Talk: Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks - David Luo, Mythic & Dr Zdeněk Přikryl, Codasip

Sign up or log in to save this to your schedule, view media, leave feedback and see who's attending!

A characteristic of the RISC-V ISA is its provision for custom extensions enabling the ISA to be tailored to the needs of a particular workload. Mythic has developed the M1076 Analog Matrix Processor (AMP) chip for implementing neural networks for applications such as intelligent camera systems, robotics, etc. The AMP includes a configurable array of tiles. Each tile consists of a large analog compute engine, which stores the neural network weights, a local SRAM memory for data being passed between the neural network nodes, an SIMD unit for processing operations not handled by the analog compute array, and a RISC-V processor for controlling the sequencing and operation of the tile. The RISC-V processor is described in an architectural language which means that it is possible to extend the core by describing additional instructions and automatically generating the SDK, RTL and verification environment. This paper describes the AMP architecture and the requirements for extending the RISC-V processor to meet the sequencing and control needs. The paper describes how custom instructions were chosen and implemented in the architecture description language rather than RTL

Speakers
DL

David Luo

Sr. Manager, RTL Design, Mythic
David Luo is an experienced IC design manager with 25 years’ experience in the semiconductor industry. He graduated from Fudan University in China and then undertook research at Auburn University graduating with a degree in VLSI, neural networks and fuzzy logic. He has had IC design... Read More →
avatar for Zdenek Přikryl

Zdenek Přikryl

CTO, Codasip
Dr. Přikryl played a major role in the research at Brno University of Technology which enabled creation of the processor development tools at Codasip. Having developed the methodology, which is based on automatic generation of hardware and software development kits from processor... Read More →



Monday December 6, 2021 4:15pm - 4:25pm PST
Room 3004/3006
  Industry Targeted Solutions
Feedback form isn't open yet.