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December 6-8, 2021 | San Fransisco, CA + Virtual
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Wednesday, December 8 • 4:30pm - 4:55pm
Architecture Design for Security: Do’s and Don’ts - Gregory T. Sullivan, Dover Microsystems, Inc.

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Having ported Dover Microsystems’ CoreGuard security product to several architectures, including RISC-V, we have some lessons learned about how well-intentioned features can make the task of implementing reliable, fine-grained security gratuitously difficult. While some of our talk will focus on subtle instruction set design tradeoffs, we also have a larger, more urgent message to convey to the RISC-V community about designing an architecture that is friendly to future, innovative security products. A non-exhaustive list of gotchas from RISC-V and other ISAs: (1) exception delegation, where was EPC stored? (2) multi-word load/stores operations paused or canceled due to interrupt or exception - what loads/stores were executed; also when are we resuming? (3) lazy register spills - too clever by half! (4) punning JAL for exception return - saves max 2 instructions, adds complexity. (4) register windows and wraparound - complexity better handled in compiler than HW. We strongly encourage a general, trace-based introspection feature to support a wide range of debugging and security products, rather than per-feature-ISA extensions that will eventually throttle the ISA due to complexity.

avatar for Greg Sullivan

Greg Sullivan

Chief Scientist, Dover Microsystems
Greg Sullivan is Chief Scientist and co-founder of Dover Microsystems. At Dover, Greg helps communicate technical concepts both internally and to customers, and contributes to design and implementation of the CoreGuard product. Earlier, Greg worked at Draper laboratory, which led... Read More →

Wednesday December 8, 2021 4:30pm - 4:55pm PST
Room 3005/3007
  Beyond the RISC-V ISA
  • Talk Type Virtual
  • Presentation Slides Attached Yes