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Tuesday, December 7 • 3:30pm - 3:55pm
AI-RISC - Custom Extensions to RISC-V for Energy-efficient AI Inference at the Edge of IoT - Vaibhav Verma, University of Virginia

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Numerous hardware accelerators have been proposed to meet the performance and energy-efficiency requirements of AI applications. But these accelerators have been developed in separate silos with little to no infrastructure for integrating these accelerators in the top-level system stack. We present AI-RISC as a solution to bridge this research gap. AI-RISC is a hardware/software codesign methodology where AI accelerators are integrated in the RISC-V processor pipeline at a fine-granularity and treated as regular functional units during the execution of instructions. AI-RISC also extends the RISC-V ISA with custom instructions which directly target these AI functional units (AFU) resulting in a tight integration of AI accelerators with the processor. AI-RISC adopts a 2-step compilation strategy where open-source TVM is used as the front-end compiler while LLVM based custom C-compiler is used as the backend along with complete SDK generation. AI-RISC enables a RISC-V based processor which supports both AI and non-AI workloads for edge applications, flexibly hot-swaps AFUs when better hardware is available and scales with new instructions as AI algorithms evolve in the future.

avatar for Vaibhav Verma

Vaibhav Verma

Student, University of Virginia
Vaibhav Verma is a graduate student at University of Virginia pursuing Ph.D. in Electrical Engineering. He received his B.E. in Electrical and Electronics Engineering from Birla Institute of Technology and Science - Pilani, India in 2013. Before starting his graduate degree, he worked... Read More →

Tuesday December 7, 2021 3:30pm - 3:55pm PST
Room 3005/3007
  Beyond the RISC-V ISA