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Tuesday, December 7 • 10:30am - 10:55am
Efficient Issue Scheduling for Hardware Multithreaded RISC-V Pipeline - Dr. Shlomo Greenberg, Ben Gurion University of the Negev & Sami Shamoon College Engineering, Beer-Sheva, Israel

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Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoid- ing CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based mul- tithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated using the standard MiBench benchmark and other common applications, demonstrating pipeline utilization improvement of up to about 26% in terms of IPC using four threads.

avatar for Shlomo Greenberg

Shlomo Greenberg

Dr., Ben-Gurion University of the Negev
Shlomo Greenberg received the B.Sc., M.Sc. (Hons.), and Ph.D. degrees from the Ben-Gurion University of the Negev, Beer-Sheva, Israel, in 1976, 1984, and 1997, respectively, all in electrical and computer engineering. He is currently a Staff Member with the Department of Electrical... Read More →

Tuesday December 7, 2021 10:30am - 10:55am PST
Room 3004/3006