RISC-V Summit

Up until now, most commercial implementations of RISC-V have focused on embedded use cases; with the emergence of RISC-V as an alternative to the ARM and Intel ecosystems, higher-end applications that include storage and the datacenter are moving into focus. This also shifts the perspective on target workloads and representative benchmarks. We show how quantitative methods can be used to assess the quality of code generation and identify and prioritize potential improvements based on hot-block analysis, dynamic instruction count metrics, and instruction histograms. The difference applicability to small benchmarks (such as Coremark, where this method identifies both a superoptimisation opportunity for the CRC functions and highlights the absence of conditional-move instructions in the RISC-V instructions set) and large benchmarks (such as SPEC, which helps to improve and mature the tools across the board) are demonstrated. The proposed methodology can provide much-needed quantitative data to the standardization of new extensions, guide future micro-architecture development and provide quality-metrics for toolchain development.