RISC-V Summit

Datacenter accelerators, especially those for ML/DL and analytics, are projected to have a high CAGR for the next 10 years. However, design teams face the challenge to come out a scalable architecture under a limited power budget and schedule. Among other tasks, they need to identify the best off-the-shelf processor IP’s, customize them to meet the performance of key computations, tightly couple them with hardwired engines, and integrate the customized processor compilers with the AI model compilers. In this talk, we will introduce Andes solutions to address the challenge of designing next-generation datacenter accelerators.