RISC-V Summit

RISC-V Vector instructions offer significant flexibility and options to configure a hardware accelerator for applications such as Datacenters and AI. Following initial cloud-based development with extensive real-world datasets, the migration to a hardware accelerator array with RISC-V vectors is redefining the software driven approach to hardware design.

This talk highlights SoC architectural exploration with multicore arrays and optimized RISC‑V processors to support early software development for vector accelerators. It introduces some of the challenges and discusses different approaches being adopted in the community/industry.