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RISC-V Summit has ended
December 6-8, 2021 | San Fransisco, CA + Virtual
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Monday, December 6 • 1:40pm - 1:50pm
Keynote: Are the RISC-V Design Freedoms Leading to RISK in Verification Quality? - Larry Lapides, Vice President Sales, Imperas Software Ltd.

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Traditional SoC projects estimate that 50-80% of the cost/effort will be for verification, but that is based the traditional approach using mainstream providers with pre-verified processor IP cores. RISC-V offers more options to SoC Developers, from developing a custom core, downloading an open-source project, selecting from one of the new IP providers, plus adding custom instructions to any of these starting points.
The flexibility of RISC-V appears to imply an increase in the DV scope of work for any SoC project with a customized RISC-V core, in this talk we will introduce the Imperas Reference Model based solutions for RISC-V processor verification.

Speakers
avatar for Larry Lapides

Larry Lapides

Vice President Sales, Imperas Software Ltd
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before... Read More →



Monday December 6, 2021 1:40pm - 1:50pm PST
Room 3008 - 3012
  Keynote Sessions
  • Presentation Slides Attached Yes