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December 6-8, 2021 | San Fransisco, CA + Virtual
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Wednesday, December 8 • 11:00am - 11:25am
Unveiling the SweRV Core EH3 - Zvonimir Bandic, Western Digital

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Western Digital has introduced a family of leading RISC-V cores branded as the SweRV Cores. The existing architectures offer the RISC-V community leading performance and power for embedded applications. With the unveiling of the SweRV EH3 core Western Digital embarks on a new trajectory. Learn about the higher performance capabilities, architectural details and timeline. During the technical talk we will discuss how to partner with Western Digital for SweRV EH3 access.  

avatar for Zvonimir Bandic

Zvonimir Bandic

Senior Director, Western Digital
Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and... Read More →

Wednesday December 8, 2021 11:00am - 11:25am PST
Room 3005/3007
  Beyond the RISC-V ISA