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December 6-8, 2021 | San Fransisco, CA + Virtual
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Tuesday, December 7 • 10:05am - 10:15am
Demo: Formal Verification of RISC-V Cores - Saša Stamenković, OneSpin

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Pre-silicon verification of processors is a challenging, time-consuming task. IP providers offering proprietary ISA cores leverage decades of effort and state-of-the-art EDA tools. RISC-V cores for commercial applications must achieve the same level of quality while facing the additional challenge of their own custom instructions of registers.

This demo session presents a fully-fledged environment for the formal verification signoff of RISC-V cores. Its main inputs are the target RTL core and a description of the custom extensions. It produces a set of assertions capturing that the RTL faithfully implements the chosen ISA with its custom extensions and nothing else. These assertions are exhaustively proven on the RTL.

avatar for Saša Stamenković

Saša Stamenković

Senior Application Engineer, OneSpin, A Siemens Business
Saša Stamenković is a senior field application engineer for OneSpin: A Siemens Business. He began his career as a co-founder of Methods2Business in Novi Sad, Serbia, where he gained his first exposure to OneSpin formal verification solutions. Saša’s passion for helping design... Read More →

Tuesday December 7, 2021 10:05am - 10:15am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater
  Demo Theater