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December 6-8, 2021 | San Fransisco, CA + Virtual
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Monday, December 6 • 10:45am - 10:55am
Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software

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This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in to the testbench to accommodate future modifications as adopters extend the core features.

Speakers
avatar for Simon Davidmann

Simon Davidmann

President & CEO, Imperas Software
Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Simon was an executive or European GM with 5 US based EDA startups including Chronologic which pioneered... Read More →
avatar for Lee Moore

Lee Moore

Senior Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →



Monday December 6, 2021 10:45am - 10:55am PST
Room 3004/3006
  Industry Targeted Solutions
  • Talk Type Virtual
  • Presentation Slides Attached Yes