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December 6-8, 2021 | San Fransisco, CA + Virtual
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Tuesday, December 7 • 10:20am - 10:30am
Demo: Brief Introduction to the 5 Levels of RISC-V Processor Verification - Kevin McDermott & Lee Moore, Imperas Software

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The open RISC-V Instruction Set Architecture (ISA) is enabling a wide range of options on the design side, to completement this a number of options can be applied to the verification tasks, since a basic proof of concept prototype may not need all the quality checks as a high volume or high reliability application. This talk will review the 5 different simulation-based DV flows, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support the most complex processors.

Speakers
avatar for Kevin McDermott

Kevin McDermott

Vice President Marketing, Imperas Software Ltd
Before joining Imperas, Kevin held a variety of senior business development, licensing, segment marketing, and product marketing roles at ARM, MIPS and Imagination Technologies focused on CPU IP and software tools. Previously Kevin was a principal analyst for IoT at ABI Research... Read More →
avatar for Lee Moore

Lee Moore

Senior Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →



Tuesday December 7, 2021 10:20am - 10:30am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater
  Demo Theater