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December 6-8, 2021 | San Fransisco, CA + Virtual
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Wednesday, December 8 • 9:30am - 9:55am
Esperanto’s Custom RISC-V ISA Extensions for Energy-Efficient Machine Learning Applications - Jayesh Iyer, Esperanto Technologies

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Jayesh Iyer, Principal Architect at Esperanto, will explain the development of the company’s custom vector/tensor extensions to the RISC-V instruction-set architecture and how these new instructions are used to implement machine-learning models for data center inferencing applications.

Attendees will learn how the extensions were selected and implemented in the company’s ET-Minion cores, what operations and data types are supported, how the extensions interact with other elements of the chip such as caches and the on-die interconnect, and how developers will be able to take advantage of the high computation and communication bandwidth delivered by Esperanto’s ET-SoC-1 “supercomputer on a chip.”

What attendees will learn:
• How Esperanto designed custom instruction-set extensions to adapt the company’s ET-Minion RISC-V core for machine-learning applications
• How developers can take advantage of these instructions and other chip-level optimizations to achieve high throughput and efficiency for these workloads

This presentation will provide actionable insight into the process of developing and using custom instruction-set extensions for RISC-V processor cores.

Speakers
avatar for Jayesh Iyer

Jayesh Iyer

Principal Architect, Esperanto Technologies
Jayesh Iyer Is a Principal Architect at Esperanto, and one of its early employees, responsible for architectural definition and performance analysis of the SOC. Prior to that, he was at Intel labs for 13 years working on advanced CPU architectures including HW/SW co-designed microprocessors... Read More →


Wednesday December 8, 2021 9:30am - 9:55am PST
Room 3004/3006