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December 6-8, 2021 | San Fransisco, CA + Virtual
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Wednesday, December 8 • 10:05am - 10:15am
Demo: RISC-V Software Debug in an Emulation Environment - Andy Meier, Siemens

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Software-enabled debug in an emulation-based verification environment is advantageous to designers working on RISC-V-based designs, as opposed to manually traversing static log files and waveforms from simulation. Because the RISC-V community’s needs are so diverse, this debug environment must be capable of managing IP from multiple providers including custom implementation of the RISC-V architecture. This presentation gives you a glimpse at what software-enabled debug options are possible for your RISC-V-based designs.

avatar for Andy Meier

Andy Meier

Product Manager, Siemens
Andy Meier is a product manager in the Scalable Verification Solutions Division at Siemens EDA. He holds a Bachelor of Science degree in Engineering and Computer Engineering from Worcester Polytechnic Institute in Worcester, Mass.

Wednesday December 8, 2021 10:05am - 10:15am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater
  Demo Theater