RISC-V Summit: Full Schedule

December 6-8, 2021 | San Fransisco, CA + Virtual
Learn More & Register Now

7:00am PST

Registration + Vaccine Verification

Monday December 6, 2021 7:00am - 6:00pm PST
Level 1 Foyer

9:00am PST

A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India

Posit arithmetic is popularly being discussed and analysed in research community about providing better accuracy and larger dynamic range than conventional IEEE 754-2008 based Floating point arithmetic. Such analysis has catalyzed the efforts in applying such new arithmetic for various applications domains viz. scientific, signal processing, AI/ML etc. This work presents a Posit Arithmetic Unit (P16, P32, P64, quire: parameterizable) enabled RISC-V processor (RV64IMAFD) architected with 6-stages in-order pipeline and FreeRTOS bootable. The RISC-V processor supports either IEEE 754-2008 FP or Posit (RISC-V F and D ISA based) arithmetic. The Posit unit has been verified with an in-house developed Posit domain specific verification suite, PositGen. RISC-V GCC software toolchain has been suitably enhanced to support Posit data representation in applications. Posit enabled RISC-V core and IEEE 754-2008 FP enabled RISC-V core have been evaluated independently with a set of computational programs and the results have been compared and analyzed for accuracy. Further, Posit and IEEE 754-2008 FPU unit has been compared and analyzed for hardware resources (area) complexity and latency.

Speakers

Vivian Desalphine

Associate Director, Centre for Development of Advanced Computing (C-DAC), Bangalore, India

Vivian Desalphine is an Associate Director at the Secure Hardware and VLSI Design (SHVD) Group at Centre for Development of Advanced Computing (C-DAC), Bangalore, India. His research interests include Computer Architecture, VLSI design and implementation, embedded processor subsystem... Read More →

Aneesh Raveendran

Principal Technical Officer, Centre for Development of Advanced Computing, Bangalore

Aneesh Raveendran is currently working as a Principal Technical Officer in Secure Hardware and VLSI Design (SHVD) Group at Centre for Development of Advanced Computing (C-DAC), Bangalore, India. His research interests are RISC Processor Architectures, Floating point unit, Posit arithmetic... Read More →

Monday December 6, 2021 9:00am - 9:25am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual

9:00am PST

XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)

XiangShan, released jointly by Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS) and Peng Cheng Laboratory (PCL), is an open-source high-performance RISC-V processor started in June 2020. It's written in Chisel hardware construction language and supports RV64GC instruction set. During the development of XiangShan, they built many open-source agile tools to speed up the development, including differential testing, simulation snapshot, RISC-V checkpoints, etc. XiangShan has been taped-out for the first time in July 2021 and is expected to have its second generation taped-out at early 2022. XiangShan has been open-sourced at GitHub and contributions are welcome. In this talk, Dr. Bao will focus on the experience in chip agile development and introduce the development tools used in the XiangShan project

Speakers

Yungang Bao

Professor, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)

Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT-CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture... Read More →

XiangShan Yungang Bao 20211206 pdf

Monday December 6, 2021 9:00am - 9:25am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

9:30am PST

Lightning Talk: Improving Performance of National Crypto Algorithms with Custom Instructions - Alexander Kozlov, CloudBEAR

In this talk we will give example of how we could improve performance of particular algorithms using custom instruction approach. We will show it on example of Russian crypto national standards. Ciphers and hash function algorithms will be considered. Steps which have to be performed to integrate instruction in microcontroller level core and out-of-order RISC-V core will be covered. As well as step required to support it in software toolchains. Performance results, tradeoffs and comparisons will be presented.

Speakers

Alexander Kozlov

CTO, CloudBEAR

Alexander Kozlov is co-founder and CTO of CloudBEAR. Alexander has more than 15 years’ experience in developing software/hardware solutions based on FPGA and ASIC design. He has Master degree an EECS from Saint-Petersburg State Polytechnical University. He started his carrier as... Read More →

Monday December 6, 2021 9:30am - 9:40am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual

9:30am PST

Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications - Shubu Mukherjee, SiFive

Modern SoC’s for ADAS and other mission critical applications employ heterogeneous architectures consisting of application processors, vision and communication DSPs, and AI accelerators; each with different ISAs, toolchains, and levels of functional safety and security. Semiconductor suppliers to these markets will greatly benefit from the simplicity of a single ISA capable of addressing the performance requirements of these varied processor blocks, whose openness facilitates achieving high levels of both functional safety and secure computing. In this presentation, SiFive will highlight the progress it has made towards delivering safety-capable RISC-V processors with all necessary features for future automotive applications.

Speakers

Shubu Mukherjee

Vice President, Architecture, SiFive

Shubu Mukherjee is a pioneer in the field of design and modeling of computer architecture. He was the 2009 recipient of the Maurice-Wilkes award, an ACM award for outstanding contributions to the field of computer architecture. He is also a Fellow of ACM and a Fellow of IEEE. Dr... Read More →

Mukherjee Automotive RISC V Summit Dec 2021 pdf

Monday December 6, 2021 9:30am - 9:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

9:45am PST

Lightning Talk: A System Level Verification and Validation Environment using SweRV - Anupam Bakshi, Agnisys, Inc.

In a SoC development cycle, a vast amount of time is consumed verifying a given specification for its functional correctness before the actual tape-out of the design. The earlier you can recreate the final environment that the IP/SoC will operate in, the faster you will tape-out. We propose an advanced verification and validation environment involving the SweRV core from Western Digital to show how to automatically generate and run reusable tests, both standard as well as custom at different levels of IP/SoC verification and validation to ensure functional accuracy of the design along with 100% out-of-the box coverage.

Speakers

Anupam Bakshi

CEO, Agnisys, Inc.

Anupam is the founder and CEO at Agnisys. He has more than three decades of experience implementing a wide range of products and services in the High Tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc... Read More →

Monday December 6, 2021 9:45am - 9:55am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type In-person

10:00am PST

Break

Monday December 6, 2021 10:00am - 10:30am PST
TBA

Breaks

10:00am PST

Expo Hall

Monday December 6, 2021 10:00am - 6:00pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Expo Hall

10:05am PST

Demo: RISC-V Successful Stories of Andes

Monday December 6, 2021 10:05am - 10:15am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type Virtual

10:20am PST

Demo: Introducing the PolarFire® SoC Smart Embedded Vision Kit - Avery Williams, Microchip

The PolarFire SoC SEV kit is the latest installment in the PolarFire SoC hardware family. Microchip will exhibit the SEV kit with the OpenVX demo while showcasing fabric-processor design partition in the PolarFire SoC. While image capture and scaling are executed in the programmable fabric, a Sobel filter implementation in OpenVX is run in the microprocessor subsystem. Come see how Microchip’s newest FPGA kit is delivering Mi-V to the masses.

Speakers

Avery Williams

Product Marketing, FPGA Business Unit, Microchip

Monday December 6, 2021 10:20am - 10:30am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person

10:30am PST

Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar, TU Dresden & Dr. William Jones, Embecosm

We present the development of a simple ISA extension to the Open Hardware Group's CV32E40P core, extending earlier work from the University of Southampton (https://youtu.be/t0Fpy4TzLUE). We have created a physical realization on the Nexys-A7 FPGA board under the 2021 Google Summer of Code program. We add a subset of just 8 instructions from the V extension to the Open Hardware Group CV32E0P core. The CV32E40P features an Auxiliary Processing Unit (APU) interface. This follows a subset of the OBI interface used to communicate with system memory. We use this interface for the accelerator. Several modifications were required to the core RTL in order to better support the architecture of the accelerator, primarily in regards to multi-cycle instructions. The accelerator and core RTL are then taken through the stages of FPGA development, starting from bitstream generation to debugging binary files on the FPGA. The result is a small RV32 core which speeds up the standard TinyMLPerf benchmark more than 5-fold. An important result for those looking to accelerate low energy AI inference at the edge and a free and open reference code base for others wishing to build on this work.

Speakers

William Jones

AI Engineer, Embecosm Limited

William Jones has a research background in computational neuroscience, with a focus on artificial neural networks and machine learning techniques. He leads Embecosm’s AI team, working on applying these machine learning and AI techniques to Embecosm's domains of interest. Dr Jones... Read More →

Veronia Iskandar

PhD researcher, TU Dresden

Veronia Iskandar is a PhD candidate in Computer Science in the Adaptive Dynamic Systems (ADS) chair at the Technical University in Dresden, Germany, since March 2020. Before joining the ADS research group, she studied Computer and Systems Engineering at Ain Shams University in Egypt... Read More →

Monday December 6, 2021 10:30am - 10:40am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual

10:30am PST

Open Hardware for the Open Cloud - Daniel Mangum, Upbound

While RISC-V is revolutionizing the world of Instruction Set Architectures by taking an open, community-based approach to development of the ISA itself, reference implementations, and the software ecosystem that surrounds it, a parallel movement is also taking place in the world of cloud computing. Similar to ISAs other than RISC-V, cloud platforms have traditionally exposed an interface for users to interact with, typically via a REST API, but the implementation details have remained proprietary. Additionally, the heterogeneous nature of cloud provider APIs has led to a disparate ecosystem of software used to interact with the platforms. In this talk we'll examine how the cloud ecosystem is experiencing a revolution similar to the open hardware movement, then explore what a future looks like when these two efforts coalesce.

Speakers

Daniel Mangum

Principal Software Engineer, Upbound

Daniel Mangum is a Principal Software Engineer at Upbound and a maintainer of Crossplane, an open source CNCF incubating project. He has served in a variety of roles in the upstream Kubernetes project, most recently as a Tech Lead of SIG Release, and is active in multiple other open... Read More →

Monday December 6, 2021 10:30am - 10:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person

10:45am PST

Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software

This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in to the testbench to accommodate future modifications as adopters extend the core features.

Speakers

Simon Davidmann

President & CEO, Imperas Software

Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Simon was an executive or European GM with 5 US based EDA startups including Chronologic which pioneered... Read More →

Lee Moore

Lead Applications Engineer, Imperas Software

Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →

Imperas Lightning Talk (Moore Davidmann) Open Source and Industrial DV (RISC V Summit)(6 Dec 2021).6a pdf

Monday December 6, 2021 10:45am - 10:55am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

11:00am PST

Lightning Talk: De-RISC, the Horizon 2020 Project that will Create the First RISC-V, Fully European Platform for Aerospace - Paco Gómez-Molinero, fentISS

The world market for aerospace computing systems faces a significant shift caused by the loss of momentum of the traditionally used instruction set architectures in the commercial domain. RISC-V offers a unique opportunity to develop EU-based products for the aerospace domain with no dependence on non-European technology or proprietary IP rights, which would impose licensing fees and export restrictions otherwise. De-RISC project brings together leading European entities within the areas of fault-tolerant microprocessors, hypervisors, embedded safety-critical software and mixed-criticality systems in an effort to commercialize a complete technology stack. The goal is to create a multicore platform for the aerospace industry based on the open RISC-V instruction set architecture together with specific features to address the needs of the target industries and to adopt modern commercial technology leveraging technology developments for other domains. This session covers concepts related to hardware Systems-on-Chip, XtratuM hypervisor, space qualification, and use cases for RISC-V based systems supporting high integrity levels, mixed-criticality, high performance, and dependability.

Speakers

Paco Gómez-Molinero

CEO, fentISS

Paco Gómez is CEO at fentISS. He holds a Master's Degree in Telecommunication Engineering by the Technical University of Madrid. He is in charged of defining and implementing the company strategy in the aerospace market and in adjacent markets for the company products. He worked... Read More →

De RISCProject LightningTalk final pdf

Monday December 6, 2021 11:00am - 11:10am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

11:00am PST

Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services

In this talk we will describe Semidynamics' vector unit implementing the RVV-010 specification and we will focus on the challenges of supporting out-of-order execution for vector instructions. We will cover the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. We will also provide an overview of the vector load/store pipeline.

Speakers

Roger Espasa

CEO, Semidynamics Technology Services SLU

Roger Espasa got his Phd in Computer Science from Universitat Politècnica de Catalunya in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Between 2002 and 2014 Roger worked at Intel developing... Read More →

2021.12.06.OOO Vectors for Summit pdf

Monday December 6, 2021 11:00am - 11:25am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

11:15am PST

Lightning Talk: Adding 32-bit Linux Support to ARIANE/CVA6 Open-source Application Core - Sébastien Jacq & Jérôme Quévremont, Thales

Together with OpenHW, Thales runs the CVA6 project, to transform ETH Zürich and University of Bologna’s ARIANE famous RISC-V application core into an industrial-grade core available as open-source for the community. From the original 64-bit ARIANE SystemVerilog design, renamed CV64A6 by OpenHW, Thales has created a 32-bit flavor, CV32A6, a resource-optimized version for embedded applications that need to support rich OSes like Linux. CV64A6 and CV32A6 share the same code base “CVA6”. In this talk, members of the CVA6 team will present the journey towards the support of Linux by CV32A6: designing a new 32-bit (Sv32) MMU, debugging the 32-bit pipeline, integrating a bootloader and Linux kernel with Buildroot, running a HW/SW integration and debugging and finally demonstrating a running Linux on a FPGA board. As a takeaway, the audience will be pointed to the open-source repositories that they can use to implement CVA6 and Linux when they return home. The next steps in this open-source project are the optimization of CV32A6 to target FPGA platforms (in addition to ASIC technologies), the addition of a few safe&secure features, more verification to get an industrial-grade IP…

Speakers

Jérôme Quévremont

RISC-V and open hardware project leader, Thales

Jérôme Quévremont is RISC-V and open hardware project leader at Thales Research and Technology (TRT), Palaiseau, France. He serves as the chair of the OpenHW Group Technical WG and the technical leader of the CVA6 (formerly ARIANE) application core project. He is also the chairman... Read More →

Sébastien Jacq

Research engineer, Thales

Sébastien Jacq is research engineer at Thales Research and Technology. He specializes in the design of digital computational architecture and in the implementation of algorithms on FPGA / SoC / MPSoC target. Sébastien is currently an actor in the RISC-V community. He actively contributes... Read More →

riscv summit 2021 sj thales pdf

Monday December 6, 2021 11:15am - 11:25am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type In-person
Presentation Slides Attached Yes

11:30am PST

Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC

The availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores. This talk presents Vitruvius, the first RISC-V vector accelerator developed at BSC for the Supercomputing domain. Vitruvius is compliant with the RISC-V vector extension specification V0.7.1. and can be easily connected to a scalar core using the Open Vector Interface (OVI) standard in a plug-and-play fashion. Vitruvius natively supports long vectors: 256 Double Precision (DP) floating-point elements in a single vector instruction. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File (VRF) and functional units (one integer, one floating-point). It adopts a novel hybrid in-order/out-of-order execution scheme, supported by vector register renaming and arithmetic/memory instruction decoupling. When configured with eight vector lanes, Vitruvius reaches a maximum frequency of 1.25 GHz when synthesized using GLOBALFOUNDRIES 22FDX FD-SOI. The silicon implementation has a total area of 1.13 mm2 and total estimated power of 1648 mW.

Speakers

Francesco Minervini

Research Engineer, Barcelona Supercomputing Center - BSC

Francesco Minervini received the MSc. and the BSc. from the University of Rome "La Sapienza" in 2018 and 2015, respectively. He has been working as an RTL Research Engineer for BSC for three years, as the main designer of the EPI (European Processor Initiative) Vector Accelerator... Read More →

Oscar Palomar Perez

Established Researcher, Barcelona Supercomputing Center - BSC

Oscar Palomar received a B.S. in Computer Science and PhD degree on Computer Architecture from the Polytechnic University of Catalonia (UPC), Spain. He joined the Computer Architecture for Parallel Paradigms research group at the Barcelona Supercomputing Center as a post-doc. There... Read More →

Final Vitruvius RISC V Summit pdf.pptx pdf

Monday December 6, 2021 11:30am - 11:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

11:30am PST

Extending RISC-V Instructions for 5G Intelligent RAN Base Stations - Gururaj Padaki & Sriram Rajagopal, EdgeQ

Current 5G architecture is undergoing a transformation towards openness to increase deployment flexibility and network dynamicity, so that networks will be able to meet the performance requirements demanded by applications such as extreme mobile broadband and massive MTC. For the first time in wireless communications, we have extended RISC-V instructions for 5G to help bring an open programmable baseband solution that will encourage new developers and partners for 5G open-RAN. The proposed architecture will be software-configurable and split between general-purpose and specialized Software Defined Radios based on a RISC-V SoC, in a way that enables ideal placement of network functions.

Speakers

Gururaj Padaki

Head PHY-Control, EdgeQ

Gururaj has about 20 years of industry experience in Application Specific Processor (ASP) /4G/5G Product Design. His career stems from designing and deploying “Bits to Antenna” for industry-defining 5G wireless systems. At EDGEQ he is responsible for the productization of the... Read More →

Sriram Rajagopal

Head System Engineering, EdgeQ

Sriram has 17 years of distinguished history as a Systems Architect for wireless communications. He brings a unique perspective to complex wireless deployments having worked on both endpoints of the network - UEs and Base stations. His career spans from designing and deploying industry... Read More →

EdgeQ RISC V Summit Dec 2021 FINAL pdf

Monday December 6, 2021 11:30am - 11:55am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

12:00pm PST

Lunch Break (Attendees on Own)

Monday December 6, 2021 12:00pm - 1:30pm PST
TBA

Breaks

1:30pm PST

Keynote: Welcome & Opening Remarks - Calista Redmond, CEO, RISC-V International

Speakers

Calista Redmond

CEO, RISC-V International

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Monday December 6, 2021 1:30pm - 1:40pm PST
Room 3008 - 3012

Keynote Sessions

1:40pm PST

Keynote: Are the RISC-V Design Freedoms Leading to RISK in Verification Quality? - Larry Lapides, Vice President Sales, Imperas Software Ltd.

Traditional SoC projects estimate that 50-80% of the cost/effort will be for verification, but that is based the traditional approach using mainstream providers with pre-verified processor IP cores. RISC-V offers more options to SoC Developers, from developing a custom core, downloading an open-source project, selecting from one of the new IP providers, plus adding custom instructions to any of these starting points.
The flexibility of RISC-V appears to imply an increase in the DV scope of work for any SoC project with a customized RISC-V core, in this talk we will introduce the Imperas Reference Model based solutions for RISC-V processor verification.

Speakers

Larry Lapides

Vice President Sales, Imperas Software

Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before... Read More →

2. Larry Lapides pdf

Monday December 6, 2021 1:40pm - 1:50pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

1:55pm PST

Keynote: Bringing RISC-V to Life: Building our Software Ecosystem - Philipp Tomsich, Founder and Chief Technologist, VRULL GmbH

Speakers

Philipp Tomsich

Chief Technologist, VRULL GmbH

Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy focused on building, enabling, and optimizing the software ecosystems for next-generation silicon solutions. Philipp brings broad experience and expertise in runtime systems (including Java... Read More →

Phillipp riscv summit keynote pdf

Monday December 6, 2021 1:55pm - 2:10pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

2:10pm PST

Keynote: The Future of RISC-V has No Limits - Dr. Yunsup Lee, Co-Founder & Chief Technology Officer, SiFIve

Learn from one of the inventors of RISC-V the technical details behind the highest performance RISC-V processor IP, and why it is so critical for the future of RISC-V. RISC-V has grown from humble academic origins into a worldwide industry standard for an immense range of commercial products. At SiFive, RISC-V has no limits.

Speakers

Dr. Yunsup Lee

Co-Founder & Chief Technology Officer, SiFIve

Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC‑V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also... Read More →

SiFive YL RISCV Summit 2021 Keynote FINAL pdf

Monday December 6, 2021 2:10pm - 2:30pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

2:30pm PST

Keynote: The Showcase of RISC-V Wins!

Join us for a fast-paced, informative, and celebratory walk-through of the RISC-V product, technical, and member accomplishments of 2021. You are guaranteed to hear about something you did not know about!

Monday December 6, 2021 2:30pm - 2:35pm PST
Room 3008 - 3012

Keynote Sessions

2:35pm PST

Keynote: Building Customized Solutions from Open-sources - Xiaoning Qi, Vice President, Alibaba Group

Diversified applications from edge to cloud demand a collaborative environment for global developers. Open-sourcing the IPs and SW platform becomes an evitable trend. Xuantie facilitates building a customized solution by opening its software stack and the processors.

Speakers

Qi Xiaoning

CEO, T-HEAD SEMICONDUCTOR

Xiaoning Qi is the Vice President of Alibaba Group. Previously, he held senior management and technical positions in companies such as Intel, designing integrated circuits and systems. He sits on the board of directors at several other international organizations including CHIPS Alliance... Read More →

Monday December 6, 2021 2:35pm - 2:45pm PST
Room 3008 - 3012

Keynote Sessions

2:45pm PST

Keynote: Diversity, Equity, and Inclusion in Open Hardware - Dr. Marjan Radi, Research Technologist Engineer, NVM Systems Architecture, Western Digital & Kim McMahon, Director of Visibility & Community Engagement, RISC-V International

The Open Hardware Diversity Alliance formed in September 2021 with a partnership between RISC-V, Chips Alliance, OpenPower Foundation, and Western Digital with a mission to provide programs to encourage participation and support the professional advancement of women and underrepresented individuals in open source hardware.

We asked ourselves:

Why are there few women and underrepresented individuals in the open hardware community?
Is it because open hardware is hard to navigate?
Is career progression a mystery?
Is it a lack of visibility of the talent in open hardware to the community?

Kim and Marjan will talk about the goals of the Alliance, upcoming programs, and how you can get involved. Sujata will join to share their experiences on how they got involved in technology and the path to success as a Technology Evangelist at Intel and a leader in the open source technology industry.

Speakers

Kim McMahon

Director of Visibility & Community Engagement, RISC-V International

Kim McMahon is the Director of Visibility & Community Engagement of RISC-V International. She comes to RISC-V with a deep background in marketing for open source and technology. She has spent her career with companies such as SGI, Cray, VMware, and the {code} Team at Dell, where she... Read More →

Dr. Marjan Radi

Research Technologist Engineer, NVM Systems Architecture, Western Digital

Dr. Marjan Radi started her high-tech career at Western Digital as an R&D Technologist in September 2017, after completing her post-doc at the University of Iowa. She holds a Bachelor of Science degree in Computer Software Engineering, Master of Science in Computer Software Engineering... Read More →

Monday December 6, 2021 2:45pm - 3:00pm PST
Room 3008 - 3012

Keynote Sessions

3:00pm PST

Break

Monday December 6, 2021 3:00pm - 3:30pm PST
TBA

Breaks

3:05pm PST

Demo: 10 Minute RISC-V Custom Instructions - Zdenek Přikryl, Codasip

Codasip will show how you can use the Studio tool to create a custom RISC-V instruction, toolchain, simulator and debug it in just 10 minutes

Speakers

Zdenek Přikryl

CTO, Codasip

Dr. Přikryl played a major role in the research at Brno University of Technology which enabled creation of the processor development tools at Codasip. Having developed the methodology, which is based on automatic generation of hardware and software development kits from processor... Read More →

RISCVSummit 2021 Demo 10 Minutes RISC V Custom Instructions pdf

Monday December 6, 2021 3:05pm - 3:15pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person
Presentation Slides Attached Yes

3:20pm PST

Demo: Containers and Kubernetes in the RISC-V Architecture - Carlos Eduardo de Paula, Red Hat

Open-source is all around us and RISC-V opened the last door for a complete open stack, hardware. Together with containers, we can have a complete cloud-native stack ready for the open-world to come.
In this talk we will see the current state of containers and container orchestration on RISC-V and a demo of Kubernetes running on the latest SiFive Unmatched platform.

Speakers

Carlos Eduardo de Paula

RISC-V Ambassador and Domain Architect, Red Hat

Carlos is a RISC-V Ambassador and works for Red Hat as a Cloud Architect designing solutions for customers and helping them into the cloud journey.He is currently creating ChiselV, a RISC-V processor written in Chisel HDL and writes about Kubernetes and containers on multiple architectures... Read More →

Monday December 6, 2021 3:20pm - 3:30pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type Virtual

3:30pm PST

YoC, an Open Operation System for IoT - Vincent Cui, Alibaba

YoC (Yun on Chip) is a full SW platform that contains the BSP, small footprint RTOS, SDKs for domain specific applications and the tools for debug. It uses RVM-CSI, a proven low-density hardware abstract layer that has been standarized in RISC-V. It also supports resource-constrained RTOS, e.g. FreeRTOS and RT-thread, provides security and is highly configurable, that could significantly reduce the time-to-market. The smart voice application is addressed as an example and to get developers started using the cloud lab and the RVB2601 devkit.

Speakers

Xiaoxia Cui

IoT Security Expert, Alibaba

Vincent Cui has been worked in embedded software industry for more than 10+ years. He is currently focusing on the IoT system software platform, that expands to specific domains such as wireless connection (BLE and WiFi), intelligent voice, graphics, multimedia and AI. He is the Vice-Chair... Read More →

Monday December 6, 2021 3:30pm - 3:55pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual

3:30pm PST

RISC-V on Edge: Porting EVE and Alpine Linux to RISC-V - Roman Shaposhnik & Kathy Giori, ZEDEDA Inc.

What is special about community-industry collaboration around an open architecture like RISC-V is that the community can join development around key kernel subsystems in parallel with the semiconductor companies and manufacturers as they are producing the new chipsets and boards. Open silicon design, open board design, and open kernel software speeds bring-up of new boards and fosters greater innovation due to the diversity of talent contributing to the technology. For many kernel developers, tackling RISC-V is becoming harder to resist now that commercially viable and scalable hardware has begun to enter the market. A private beta program launched by the BeagleBoard Foundation in March 2021 placed an affordable, yet powerful prototype RISC-V board into the hands of Roman Shaposhnik. What did Roman do? He joined a diverse team of software and hardware hackers to tackle bringing up Linux on the new board. In this talk, Roman will tell you about his experience porting Alpine Linux and LF Edge EVE-OS to the new RISC-V architecture.

Speakers

Roman Shaposhnik

Founder, ZEDEDA Inc.

A member of the lost tribes of Sun microsystems (still wöndering in the valley) Co-founder & CHO @ZEDEDAEdge VP Legal, Board @TheASF & @LF_Edge AKA 谢罗文 @ 阿帕奇 Roman is a well known and acknowledged expert and visionary in Open Source strategy and execution. When co-founding... Read More →

Kathy Giori

Director of Product Engineering, ZEDEDA

Kathy Giori, Director of Product Engineering at Zededa Inc., is actively using and promoting LF Edge project EVE. She has worked in technology for over 30 years. Kathy also volunteers her time as a mentor of the TechWomen program, and to support and evangelize several open source... Read More →

LF RISC V 2021 Roman Kathy pdf

Monday December 6, 2021 3:30pm - 3:55pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

4:00pm PST

Lightning Talk: Accelerating Real-World AI Software using the RISC-V Vector Extension - Colin Davidson & Alastair Murray, Codeplay Software

Software developers and processor designers are looking to accelerate the latest AI and machine learning applications requiring parallel processing architectures. The RISC-V Vector (RVV) extension is a recent addition to the RISC-V ISA providing the basis for translating vector and scalar based computation onto parallel processor cores. RVV defines a way to accelerate AI computation, e.g., tensor datasets, in parallel on multi-core processors. However, the extension only defines the interface, and still needs to be implemented at the compiler level to enable the division of workload across different processors. This presentation will show how Codeplay has enabled neural network software algorithms to execute on the RVV extension with automatic vectorization; all using open standards including SYCL, and open-source software. We will explore the practical steps needed to implement RVV using a Spike simulator, the required software frameworks, libraries, and toolkits to bring together, and how to enable a complex application using a real-world neural network.

Speakers

Alastair Murray

VP Product Engineering, Codeplay Software

Alastair is the VP of Product Engineering at Codeplay. He oversees the development of Codeplay's products, covering compilers and language runtimes for heterogeneous processors. He is also involved in the development of the OpenCL and SYCL open standards from Khronos.

Colin Davidson

Principal Engineer, Codeplay

Colin Davidson is a Principal Software Engineer at Codeplay with over 20 years of broad experience in developing software for system on chip processors – working at all levels, from writing assembly to producing compilers to developing graphic drivers and toolchains. Prior to Codeplay... Read More →

Codeplay Software Alastair Murray Accelerating NN on RVV pdf

Monday December 6, 2021 4:00pm - 4:10pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

4:00pm PST

Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA

Increasing the performance and efficiency of a RISC-V designs can be done by moving compute intensive functions from software, running on the CPU, into hardware accelerators. These accelerators can take the form of new instructions, co-processors, or bus based peripherals. One way to create this type of accelerator is to use High-Level Synthesis (HLS). HLS takes a C or C++ function and synthesizes a functionally equivalent Register Transfer Level (RTL) hardware description. This RTL description can be used to create the hardware accelerator for an ASIC or FPGA. This session will show you how to create different types of accelerators using HLS and how to integrate them into RISC-V processor designs. An AI inferencing algorithm and a an encryption algorithm will be used as examples to show how the accelerator can impact the performance and power consumption of a RISC-V design.

Speakers

Russell Klein

Engineer, Siemens EDA

Russell Klein is a program director with Siemens EDA in the High-Level Synthesis group. He is focused on algorithm acceleration using HLS. By off-loading complex or compute intensive functions from the CPU into hardware accelerators the performance and power consumption of the system... Read More →

Monday December 6, 2021 4:00pm - 4:25pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person

4:15pm PST

Lightning Talk: Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks - David Luo, Mythic & Dr Zdeněk Přikryl, Codasip

A characteristic of the RISC-V ISA is its provision for custom extensions enabling the ISA to be tailored to the needs of a particular workload. Mythic has developed the M1076 Analog Matrix Processor (AMP) chip for implementing neural networks for applications such as intelligent camera systems, robotics, etc. The AMP includes a configurable array of tiles. Each tile consists of a large analog compute engine, which stores the neural network weights, a local SRAM memory for data being passed between the neural network nodes, an SIMD unit for processing operations not handled by the analog compute array, and a RISC-V processor for controlling the sequencing and operation of the tile. The RISC-V processor is described in an architectural language which means that it is possible to extend the core by describing additional instructions and automatically generating the SDK, RTL and verification environment. This paper describes the AMP architecture and the requirements for extending the RISC-V processor to meet the sequencing and control needs. The paper describes how custom instructions were chosen and implemented in the architecture description language rather than RTL

Speakers

David Luo

Sr. ASIC Design Manager, Mythic Inc.

David Luo is an experienced IC design manager with 25 years’ experience in the semiconductor industry. He graduated from Fudan University in China and then undertook research at Auburn University graduating with a degree in VLSI, neural networks and fuzzy logic. He has had IC design... Read More →

Zdenek Přikryl

CTO, Codasip

RISCVSummit 2021 PPT mythic codasip rev.6 pdf

Monday December 6, 2021 4:15pm - 4:25pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type In-person
Presentation Slides Attached Yes

4:30pm PST

Advanced Interrupt Architecture and Advanced CLINT - Anup Patel, Western Digital & John Hauser, Independent Researcher

The existing RISC-V platforms only support wired interrupts, machine-level timer interrupts and machine-level software interrupts in hardware hence there is no hardware support for message signaled interrupts (MSIs), MSI virtualization, and supervisor-level software interrupts. The advanced interrupt architecture (AIA) specification defines new interrupt controllers to support wired interrupts, MSIs and MSI virtualization in manner scalable for large number of HARTs. The advanced core local interruptor (ACLINT) specification defines separate devices for machine-level timer interrupts, machine-level software interrupts, and supervisor-level software interrupts in a manner backward-compatible for existing RISC-V platforms. The AIA and ACLINT specifications collectively address interrupt and timer requirements of different classes of RISC-V platforms.

Speakers

Anup Patel

Technologist, Western Digital Corporation

Anup Patel is an open-source enthusiast with primary interest in hypervisors, firmware, and Linux kernel. He has 15+ years of experience developing system level software across architectures. He is part of the Western Digital system software research group which does lot of open-source... Read More →

John Hauser

human, self

John Hauser is an independent computer architect, programmer, and researcher, with interests in hardware, computer languages, compilers, support libraries, low-level system software, and computer arithmetic. He received his Ph.D. in computer architecture from the University of California... Read More →

AIA and ACLINT v4 pdf

Monday December 6, 2021 4:30pm - 4:55pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

4:30pm PST

Hard Real-Time vs High Performance Real-Time Applications on PolarFire SoC - Hugh Breslin, Microchip Technology

Did you know there are different types of real-time implementations? Yes, not all real-time implementations are the same, and not all of them are deterministic. Come along and learn about what these are and how you can implement them on the five-core RISC-V based PolarFire SoC FPGA. In this session we'll look at what real-time really means, the different offerings, how to decide on the right real-time for you and how to implement them.

Speakers

Hugh Breslin

Systems Engineer, Microchip

Hugh Breslin is an Design Engineer at Microchip where he has had a focus on the test and verification of soft RISC-V SoCs, along with application development, system development and training for hardened SoC FPGAs and emulation platforms. Hugh also has a strong focus on software where... Read More →

r1 v1 210611 CORP PPT Mi V Virtual Summit Conference Presentation Realtime 2 HB pdf

Monday December 6, 2021 4:30pm - 4:55pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

4:55pm PST

Break

Monday December 6, 2021 4:55pm - 5:55pm PST
TBA

Breaks

5:05pm PST

Demo: Hands-on with SiFive Performance P550 and SiFive Freedom Studio - Joshua Smith, SiFive

Speakers

Joshua Smith

Senior Principal RISC-V Core Designer, SiFive

RISC V Summit 2021 Demo Slides V4 pptx

Monday December 6, 2021 5:05pm - 5:15pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person
Presentation Slides Attached Yes

5:30pm PST

Scavenger Hunt Prize Drawing

Complete the Expo Hall Scavenger Hunt card (available in the RISC-V Lounge) during the day, and join us to find out if you win the prize drawing! Must be present to win.

Monday December 6, 2021 5:30pm - 5:45pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Expo Hall

8:00am PST

Registration + Vaccine Verification

Tuesday December 7, 2021 8:00am - 6:00pm PST
Level 1 Foyer

Registration

9:00am PST

Support for Non-Coherent I/O Devices in RISC-V - Greg Favor & David Kruckemyer, Ventana Micro Systems

The current RISC-V ISA privilege specification only defines a broad physical memory attribute (PMA) mechanism to implement non-cacheable memory regions for any non-coherent I/O devices. While this is an acceptable approach in an embedded world, it is not sufficient for modern-day systems where the number of programmable PMAs will not scale. On other hand, having a fully coherent system is not always feasible due to design costs in spite of performance advantages. Thus, any platform with non- coherent I/O devices relies on the software managed coherency, a widely adopted approach in today's industry. The software can manage coherency either by accessing the memory in such a way that it is never cached or use cache maintenance instructions for cacheable memory. The Svpbmt(Page Based Memory Type) extension was recently proposed to provide a solution to the first approach while a set of CMO(Zicbom, Zicboz, and Zicbop) extensions are the solution to the second approach. These proposed extensions allow the platform vendors to build cost-effective RISC-V systems that are truly on par with other ISAs. This talk will outline the technical details and current status of both extensions.

Speakers

Greg Favor

CDO, Ventana Micro Systems

Greg has been architecting and designing microprocessors for 38 years, both at startups and large companies, and across many architectures including x86, PowerPC, ARMv8, and now RISC-V. Most recently this includes being co-founder and CTO of Ventana Micro Systems, which is developing... Read More →

David Kruckemyer

Principal Engineer, Ventana Micro Systems, Inc.

David is a Principal Engineer and System Architect at Ventana Micro Systems, leading the development of the RISC-V-based processor cluster and chiplet architecture for the company's products. Outside of Ventana, he is currently active in multiple RISC-V task groups, and he previously... Read More →

Support for Non Coherent IO Devices in RISC V pdf

Tuesday December 7, 2021 9:00am - 9:25am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

9:00am PST

Performance Monitoring in RISC-V using perf - Atish Patra, Western Digital

Performance analysis using a dedicated hardware performance monitoring unit(PMU) has become ubiquitous in the modern era of computing. A PMU unit consists of several programmable registers that can be used to monitor micro-architectural information using userspace tools such as perf. This was one of the key missing pieces in RISC-V software ecosystem until now. Linux kernel for RISC-V had a very basic perf support due to the missing features in RISC-V ISA. However, an SBI PMU extension and ISA extension ("SScofpmf") were recently proposed. This allows developing a RISC-V platform that is on par with any other ISA in terms of perf capabilities including virtualization support. The SBI PMU extension also added support for a set of novel firmware counters to allow users to gain insight into firmware data during performance analysis. Linux kernel and firmware support for both the proposed extension are under development. This talk will provide the details of these extensions. It will also describe the Linux perf subsystem architecture and Linux RISC-V perf driver that leverages these extensions. In the end, a live demonstration of the full capabilities of perf will be shown using Qemu.

Speakers

Atish Patra

Technologist, Western Digital

Atish is a Linux kernel engineer working at Western Digital system software research. He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers. He is also the co-maintainer of OpenSBI, the open source run time firmware for... Read More →

Perf on riscv summit atish pdf

Tuesday December 7, 2021 9:00am - 9:25am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type Virtual
Presentation Slides Attached Yes

9:30am PST

Continuous Innovation in Embedded RISC-V Processors - Drew Barbier, SiFive

The market demands for small, secure, programmable microcontrollers has created the need for a modern, scalable RISC-V embedded processors. In this talk, Drew Barbier will discuss how SiFive has significantly enhanced its offerings in the 32 and 64 bit embedded scalar processor space, and will unveil the new 6-Series of SiFive processors designed to address a wide range of 32-bit and 64-bit design needs.

Speakers

Drew Barbier

Senior Director, Product Management, SiFive

Drew has worked in the Semiconductor industry for more than 15 years in a number of engineering and customer-facing roles. Drew joined SiFive in early 2017 and is Senior Director of Product Management responsible for the RISC-V Core IP portfolio.

21G3 2021 RISC V Summit New Format rev3 pdf

Tuesday December 7, 2021 9:30am - 9:55am PST
Room 3005/3007

Industry Targeted Solutions

Talk Type In-person
Presentation Slides Attached Yes

9:30am PST

ACPI for RISC-V: Enabling Server Class Platforms - Sunil V L, Ventana Micro Systems

The "Advanced Configuration and Power Interface" (ACPI) is the major platform requirement to get server OEMs and multiple OS vendors supported on RISC-V. Due to this and few other requirements, the RISC-V platform specification will mandate ACPI as the hardware discovery mechanism for server extension. This talk will focus on how ACPI can be enabled for RISC-V, what updates are required in the ACPI specification for RISC-V, Proof of Concept (POC) of the basic ACPI enablement in RISC-V Linux, issues faced during POC, and pending items.

Speakers

Sunil V L

Principal Software Engineer, Ventana Micro Systems Inc.

Sunil is a software engineer at Ventana Micro Systems with 18 years of experience in Firmware and Operating Systems development. Sunil is the current acting vice-chair for the Platform Runtime Services TG and leads the UEFI/ACPI efforts for RISC-V.

RISCVSummit 2021 ACPI Sunil final pdf

Tuesday December 7, 2021 9:30am - 9:55am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type Virtual
Presentation Slides Attached Yes

10:00am PST

Break

Tuesday December 7, 2021 10:00am - 10:30am PST
TBA

Breaks

10:00am PST

Expo Hall

Tuesday December 7, 2021 10:00am - 6:00pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Expo Hall

10:05am PST

Demo: Formal Verification of RISC-V Cores - Saša Stamenković, OneSpin

Pre-silicon verification of processors is a challenging, time-consuming task. IP providers offering proprietary ISA cores leverage decades of effort and state-of-the-art EDA tools. RISC-V cores for commercial applications must achieve the same level of quality while facing the additional challenge of their own custom instructions of registers.

This demo session presents a fully-fledged environment for the formal verification signoff of RISC-V cores. Its main inputs are the target RTL core and a description of the custom extensions. It produces a set of assertions capturing that the RTL faithfully implements the chosen ISA with its custom extensions and nothing else. These assertions are exhaustively proven on the RTL.

Speakers

Saša Stamenković

Senior Application Engineer, OneSpin, A Siemens Business

Saša Stamenković is a senior field application engineer for OneSpin: A Siemens Business. He began his career as a co-founder of Methods2Business in Novi Sad, Serbia, where he gained his first exposure to OneSpin formal verification solutions. Saša’s passion for helping design... Read More →

OneSpin360ProcessorVerificationApp RISC V Summit pdf

Tuesday December 7, 2021 10:05am - 10:15am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person
Presentation Slides Attached Yes

10:20am PST

Demo: Brief Introduction to the 5 Levels of RISC-V Processor Verification - Kevin McDermott & Lee Moore, Imperas Software

The open RISC-V Instruction Set Architecture (ISA) is enabling a wide range of options on the design side, to completement this a number of options can be applied to the verification tasks, since a basic proof of concept prototype may not need all the quality checks as a high volume or high reliability application. This talk will review the 5 different simulation-based DV flows, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support the most complex processors.

Speakers

Kevin McDermott

Vice President Marketing, Imperas Software Ltd

Before joining Imperas, Kevin held a variety of senior business development, licensing, segment marketing, and product marketing roles at ARM, MIPS and Imagination Technologies focused on CPU IP and software tools. Previously Kevin was a principal analyst for IoT at ABI Research... Read More →

Lee Moore

Lead Applications Engineer, Imperas Software

Imperas RISC V Theater Talk (McDermott) RISC V Processor Verification RISC V Summit 2021 pdf

Tuesday December 7, 2021 10:20am - 10:30am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person
Presentation Slides Attached Yes

10:30am PST

Efficient Issue Scheduling for Hardware Multithreaded RISC-V Pipeline - Dr. Shlomo Greenberg, Ben Gurion University of the Negev & Sami Shamoon College Engineering, Beer-Sheva, Israel

Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoid- ing CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based mul- tithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated using the standard MiBench benchmark and other common applications, demonstrating pipeline utilization improvement of up to about 26% in terms of IPC using four threads.

Speakers

Shlomo Greenberg

Dr., Ben-Gurion University of the Negev

Shlomo Greenberg received the B.Sc., M.Sc. (Hons.), and Ph.D. degrees from the Ben-Gurion University of the Negev, Beer-Sheva, Israel, in 1976, 1984, and 1997, respectively, all in electrical and computer engineering. He is currently a Staff Member with the Department of Electrical... Read More →

Tuesday December 7, 2021 10:30am - 10:55am PST
Room 3004/3006

Beyond the RISC-V ISA

Talk Type Virtual

10:30am PST

RISC-V Compatible Processor IP by Syntacore: Compact Open-source MCU to Multicore Linux - John Hartley, Syntacore

We describe family of the state-of-the-art RISC-V compatible microprocessor core IP developed by Syntacore with specific focus on details of our 64bit product line and roadmap. SCRx family includes nine cores with comprehensive features targeted at different applications: from compact SCR1 MCU core, which is one of the first fully open industry-grade RISC-V compatible cores (available since 2017) to efficient Linux-capable 64bit multicore SCR7. Different cores can be used together in heterogeneous multicore clusters with atomics and memory coherency. SCRx cores deliver competitive performance at low power already in baseline configurations. On the top, Syntacore provides a one-stop workload-specific processor customization service to enable customer designs’ differentiation via significant performance and efficiency boost. Industry-standard interfacing options support (AHB, AXI, ACE) enables seamless integration with existing designs. In the session, we detail cores features, benchmarks and collateral availability and highlight new additions to the product line.

Speakers

John Hartley

Chief Commercial Officer, Syntacore

Mr. Hartley has over 28 years of experience in the semiconductor industry, having held senior sales and marketing positions in Europe, Asia and the Americas at companies such as Microchip, Tundra Semiconductor (now IDT), PLX (now Broadcom) and UltraSoC (now Siemens Mentor). Most recently... Read More →

syntacore riscv summit pdf

Tuesday December 7, 2021 10:30am - 10:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

11:00am PST

Lightning Talk: RISQV-HT: A RISC-V Microcontroller Delivering Post-Quantum Secure Encryption - and Hardware Trojans - Alexander Hepp, Technical University of Munich

Empowering electronic devices to support Post-Quantum Cryptography (PQC) is a challenging task. Especially for low cost and resource constraint devices, hardware acceleration is usually required. The speaker presents RISQV-HT, an enhanced RISC-V device that integrates a set of powerful tightly coupled accelerators to speed up lattice and isogeny-based PQC. The RISC-V ISA is extended with 41 new instructions and performs roughly 10 times faster than a software solution when encrypting with Kyber and 21 times faster when encrypting with SIKE.

As a twist, four hardware Trojans were inserted into the final chip, threatening the security properties of integrity, confidentiality and availability. The speaker shows how to detect such Trojans with tape-out-tools and reverse engineering.

The RISQV-HT was implemented in ASIC technology and taped-out at the end of 2020.

Speakers

Alexander Hepp

Research Assistant, Technical University of Munich

Alexander Hepp received M.S in electrical and computer engineering from Technical University of Munich in 2019. Currently he is a research assistant and doctoral candidate at the Chair of Security in Information Technology at the Technical University of Munich. His current research... Read More →

RISQV HT Hepp 2021 12 07 pdf

Tuesday December 7, 2021 11:00am - 11:10am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

11:00am PST

The Future of RISC-V Heterogeneous Embedded Virtualization Architectures - Sandro Pinto & José Martins, Universidade do Minho

Today’s embedded industries exhibit a strong trend towards consolidation. Virtualization is the de facto technology used to achieve this goal, since (i) it provides strong isolation between partitions and (ii) eases the porting and integration engineering costs. However, a single hypervisor might not be suited for the heterogeneous requirements of different partitions. This results in the selection of feature-rich hypervisors with large TCBs, typically consisting of the system’s single point of failure. In this talk, we share our experience while implementing the latest RISC-V (i) Hypervisor and (ii) enhanced PMP (Smepmp) extensions on the RISC-V CVA6 core, and we explain how these extensions can be synergically leveraged to implement a novel heterogeneous partitioning and virtualization architecture with enhanced security and safety guarantees. In this architecture, a hardened implementation of OpenSBI domains is used to partition system resources (i.e., memory, peripherals, interrupts), enabling the deployment of distinct hypervisors per partition, according to its requirements. We end with an illustration of possible use cases and a discussion on how to orchestrate such systems.

Speakers

Sandro Pinto

Associate Research Professor, University of Minho

Sandro Pinto is an Associate Research Professor at the University of Minho, Portugal. He holds a Ph.D. in Electronics and Computer Engineering. Sandro has a deep academic background and several years of industry collaboration focusing on operating systems, virtualization, and security... Read More →

José Martins

PhD Student, University of Minho

José Martins is a Ph.D. student and teaching assistant at the University of Minho, Portugal. José holds a Master’s in Electronics and Computer Engineering. José has a significant background in operating systems and computer architecture for embedded systems. Over the last few... Read More →

riscv het virt arch@riscvsummit21 v1.0.0 pdf

Tuesday December 7, 2021 11:00am - 11:25am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type In-person
Presentation Slides Attached Yes

11:15am PST

Lightning Talk: Enabling Software Emulation for RISC-V Heterogeneous Cores Architecture - Cui Jin & Ley Foon Tan, StarFive Technology

RISC-V has a lot of optional extensions following different version specifications. When integrating these heterogenous cores in a hybrid architecture SoC, usually it brings a lot of issues for software stacks. For instance, the big core and little core have different version of F extension, or the big core supports V extension while the small core does not. In such scenario, software stack developers have more concern to support such heterogenous architecture and enable the development and verification far ahead of hardware available. In this proposal, QEMU is modified for such purpose to assist developer to build this hybrid architecture with desired configurations and run software stack on it. With the modifications, a Linux running in AMP way is also shown as an example on this emulation platform. With Linux kernel has per-core capabilities/extensions to be identified (in this proposal, the V and non-V extension is tested), the AMP (relative to SMP) is successfully running with vector and non-vector applications mixed under the normal kernel scheduling.

Speakers

Cui Jin

Principle Engineer, StarFive International Pte. Ltd.

Cui Jin is working as a principal engineer in architecture team of StarFive, working on RISC-V SoC micro-architecture modelling and simulation. Before joining StarFive, he has more than 10 year industrial experience, working as a principal engineer in Huawei Singapore Research Centre... Read More →

Ley Foon Tan

Senior Staff Engineer, StarFive Technology

Ley Foon Tan is working as a senior staff engineer in the software team of StarFive Technology, working on RISC-V Linux kernel and device drivers development. Prior to StarFive, she worked as a staff software engineer in Intel and Altera. She was the former maintainer of Intel Nios... Read More →

Enabling Software Emulation for RISC V Heterogeneous Cores Architecture pdf

Tuesday December 7, 2021 11:15am - 11:25am PST
Room 3005/3007

Software Stack Integration and Development Tools

Talk Type Virtual
Presentation Slides Attached Yes

11:30am PST

Accelerating AI and non-AI Workloads with 1000+ Energy-Efficient RISC-V Cores on a Single Chip - Art Swift, Esperanto Technologies

Art Swift, President and CEO, will explain the development of the company’s energy-efficient “Supercomputer-on-a-chip”, it’s architecture and strengths at addressing a wide range of AI and non-AI workloads. A sample use case will be discussed which will highlight the ability to support embedding tables in large models

Speakers

Art Swift

President and CEO, Esperanto Technologies

Art Swift has 30 plus years of executive-level experience in the tech and microprocessor industry, including as CEO at low power processor chip maker Transmeta, as president of MIPS, a leading provider of microprocessor IP, as CEO of Wave Computing, a pioneer in dataflow computing... Read More →

Tuesday December 7, 2021 11:30am - 11:55am PST
Room 3004/3006

Beyond the RISC-V ISA

Talk Type In-person

11:30am PST

RISC-V Debug in the OS-A Platform - Paul Donahue, Ventana Micro Systems

Debug infrastructure is a critical element in any system. Debug features within every layer of the software stack provide the needed visibility toward finding issues in any system. Paul Donahue is the vice-chair of the RISC-V Debug Task Group and author of the requirements for debug support that have recently been added to the OS-A platform specification. In this talk he will provide an overview of the debug architecture features that are in OS-A. These features provide a consistent minimum feature set that debuggers (both native and external) can rely on for debugging everything from the first instruction after reset to operating systems and hypervisors to user applications.

Speakers

Paul Donahue

Principal Engineer, Ventana Micro Systems

Paul Donahue has over 25 years of experience with computer architecture and design verification. He has been involved with several task groups since becoming active in RISC-V in 2019 and is currently vice-chair of the Debug Task Group.

DebugSlides pdf

Tuesday December 7, 2021 11:30am - 11:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

12:00pm PST

Lunch Break (Attendees on Own)

Tuesday December 7, 2021 12:00pm - 1:30pm PST
TBA

Breaks

1:30pm PST

Keynote: State of the Union - Krste Asanović, Professor, EECS Dept, U.C Berkeley / Chief Architect and Co-Founder, SiFive Inc.

Speakers

Krste Asanovic

Chair, RISC-V International

Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded... Read More →

1. Krste Asanović pdf

Tuesday December 7, 2021 1:30pm - 1:45pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

1:45pm PST

Keynote: Beefing Up the Datacenter Accelerators - Charlie Su, President and CTO, Andes Technology

Datacenter accelerators, especially those for ML/DL and analytics, are projected to have a high CAGR for the next 10 years. However, design teams face the challenge to come out a scalable architecture under a limited power budget and schedule. Among other tasks, they need to identify the best off-the-shelf processor IP’s, customize them to meet the performance of key computations, tightly couple them with hardwired engines, and integrate the customized processor compilers with the AI model compilers. In this talk, we will introduce Andes solutions to address the challenge of designing next-generation datacenter accelerators.

Speakers

Charlie Su

President and CTO, Andes Technology

Dr. Charlie Su is the co-founder, President and CTO of Andes Technology, where he has been in charge of engineering and marketing since the company was founded in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA for the first 12 years before... Read More →

2021 RISCV Summit Andes Keynote CharlieSu pdf

Tuesday December 7, 2021 1:45pm - 1:55pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

1:55pm PST

Keynote Panel: RISC-V Momentum at Data Center Scale - Balaji Baktha, Ventana (Moderator); Sumit Gupta, Google; Jing Yang, Alibaba; Roger Espasa, Semidynamics Technology Services; Bapi Vinnakota, Open Compute Project ODSA Project Lead

RISC-V has hit the big leagues! Join this panel session to hear first hand from industry leaders on enterprise class RISC-V momentum from back office to hyperscale. Learn why RISC-V has been chosen time and again for technical flexibility, business opportunity, and strategic longevity.

Moderators

Balaji Baktha

President & CEO, Ventana Micro Systems

Balaji Baktha is the founder, chairman and CEO of Ventana Micro Systems. He is an experienced semiconductor executive and serial technology entrepreneur and investor. Previously, Balaji founded Veloce Technologies, the world’s first 64-bit ARM based high performance processor. Prior... Read More →

Speakers

Bapi Vinnakota

Open Compute Project ODSA Project Lead, OCP

Roger Espasa

CEO, Semidynamics Technology Services SLU

Jing Yang

VP of Ecosystem of T-head & Sales Head, Alibaba Group

Jing Yang received her Ph.D. and Master in EECS from UC Berkeley. She is currently the VP of Ecosystem of T-head at Alibaba and sales head. Her current job focuses on building ecosystem for RISC-V, executing strategy across cloud and IoT. She is taking the lead to establish business... Read More →

Sumit Gupta

Google

Tuesday December 7, 2021 1:55pm - 2:20pm PST
Room 3008 - 3012

Keynote Sessions

2:25pm PST

Keynote: Microchip and the Expanding RISC-V Universe - Ted Speers, Technical Fellow, Microchip

Microchip Technology Inc. is leading the development of mass market availability of RISC-V ISA designs. We are making rapid progress advancing our Mi-V partner ecosystem in support of our PolarFire® SoC family of RISC-V-based SoC FPGAs, now in production. The RISC-V ecosystem comprises development tools, real-time operating systems, rich operating systems and middleware. The ecosystem is comprised of well-established commercial providers and open-source solutions including a hardware and software services network to speed developers’ time to market. Attend our keynote to learn about the scale of this ecosystem and how we are delivering on our vision of bringing RISC-V to the masses.

Speakers

Ted Speers

Technical Fellow, Microchip

Ted Speers is a technical fellow with Microchip Technology’s FPGA business unit, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. Ted is a RISC-V leader and evangelist and has served on the Board of Directors of RISC-V International... Read More →

Tuesday December 7, 2021 2:25pm - 2:35pm PST
Room 3008 - 3012

Keynote Sessions

2:35pm PST

Keynote: The Showcase of RISC-V Wins!

Tuesday December 7, 2021 2:35pm - 2:40pm PST
Room 3008 - 3012

Keynote Sessions

2:40pm PST

Keynote: Profiles and Platforms: RISC-V Convergence - Greg Favor, CTO, Ventana Micro Systems

Speakers

Greg Favor

CDO, Ventana Micro Systems

6. Greg Favor pdf

Tuesday December 7, 2021 2:40pm - 3:00pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

3:00pm PST

Break

Tuesday December 7, 2021 3:00pm - 3:30pm PST
TBA

Breaks

3:05pm PST

Demo: Hands-on with SiFive Performance P550 and SiFive Freedom Studio - John Ingalls, SiFive

Speakers

John Ingalls

Principal Engineer, SiFive

Tuesday December 7, 2021 3:05pm - 3:15pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person

3:20pm PST

Demo: How Software can Enable your Next RISC-V Device - Jeff Hancock, Siemens Embedded

Are you considering leveraging RISC-V in your next design? How would you implement your software when targeting RISC-V? Before you decide to move your next embedded project to RISC-V, know how to get the most out of this innovative technology. During this session, you will learn about some runtime software insights you need to successfully develop and deploy RISC-V-based devices. This includes toolchains, RTOS, and Linux to enable your embedded applications to take maximum advantage of RISC-V hardware.

Speakers

Jeff Hancock

Senior Product Manager, Siemens Embedded

Jeff Hancock is a Senior Product Manager for Siemens Embedded, a segment of Siemens Digital Industries Software. Over the last 20 years, Jeff has held numerous roles in the Embedded space. Jeff earned his Bachelor of Science degree in Electrical Engineering Technology from Purdue... Read More →

Siemens Embedded RISCV Software Enablement pdf

Tuesday December 7, 2021 3:20pm - 3:30pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type Virtual
Presentation Slides Attached Yes

3:30pm PST

AI-RISC - Custom Extensions to RISC-V for Energy-efficient AI Inference at the Edge of IoT - Vaibhav Verma, University of Virginia

Numerous hardware accelerators have been proposed to meet the performance and energy-efficiency requirements of AI applications. But these accelerators have been developed in separate silos with little to no infrastructure for integrating these accelerators in the top-level system stack. We present AI-RISC as a solution to bridge this research gap. AI-RISC is a hardware/software codesign methodology where AI accelerators are integrated in the RISC-V processor pipeline at a fine-granularity and treated as regular functional units during the execution of instructions. AI-RISC also extends the RISC-V ISA with custom instructions which directly target these AI functional units (AFU) resulting in a tight integration of AI accelerators with the processor. AI-RISC adopts a 2-step compilation strategy where open-source TVM is used as the front-end compiler while LLVM based custom C-compiler is used as the backend along with complete SDK generation. AI-RISC enables a RISC-V based processor which supports both AI and non-AI workloads for edge applications, flexibly hot-swaps AFUs when better hardware is available and scales with new instructions as AI algorithms evolve in the future.

Speakers

Vaibhav Verma

Student, University of Virginia

Vaibhav Verma is a graduate student at University of Virginia pursuing Ph.D. in Electrical Engineering. He received his B.E. in Electrical and Electronics Engineering from Birla Institute of Technology and Science - Pilani, India in 2013. Before starting his graduate degree, he worked... Read More →

AI RISC RISCVSummit 2021 pdf

Tuesday December 7, 2021 3:30pm - 3:55pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

3:30pm PST

Sail Specification for RISC-V P-Extension - Bow-Yaw Wang, Academia Sinica, Taiwan & Jenq-Kuen Lee, National Tsing Hua University, Taiwan

RISC-V P-extension (RVP) is designed for digital signal processing (DSP) applications on RISC-V instruction set architecture. RVP supports parallel processing with 325 new instructions. Among them, 173 Single-Instruction-Multiple-Data (SIMD) instructions are added. These instructions divide general purposed registers into 8-, 16-, 32-, or 64-bit chunks and compute an arithmetic function in parallel. RVP also contains special instructions for DSP such as cross multiplication and saturated computation. The RVP specification is a text document maintained by the RVP work group. We present a Sail specification for RVP in this work. To reduce manual and maintenance efforts, tedious Sail specifications for binary encoder/decoder and assembly mnemonics are generated automatically. We explain how dependent-type programming in Sail simplifies our semantic functions for RVP. Writing semantic functions for 325 instructions in RVP is still tedious and prone to errors. Inconsistency between the textual RVP specification and our Sail specification can be embarrassing. Using Spike, we present a workflow to validate our Sail specification for the 325 instructions defined in RVP.

Speakers

Bow-Yaw Wang

Research Fellow, Academia Sinica

Bow-Yaw Wang is a Research Fellow in Institute of Information Science, Academia Sinica, Taiwan. He received his Ph.D in University of Pennsylvania, 2001. His research interest is logic and its application in computer science. He mainly works on formal verification. In the past, he... Read More →

Jenq-Kuen Lee

Professor, National Tsing-Hua University, Taiwan

Jenq-Kuen Lee received the B.S. degree in computer science from National Taiwan University in 1984. He received the M.S. and Ph.D. degrees in 1991 and 1992, respectively, in computer science from Indiana University. He is now a professor at National Tsing-Hua University, Taiwan, where... Read More →

Sail Spec for RVP pdf

Tuesday December 7, 2021 3:30pm - 3:55pm PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type Virtual
Presentation Slides Attached Yes

4:00pm PST

Exploring the Zce Code-size Reduction ISA Extension - Tariq Kurd, Huawei UK

Tariq, the chair of code-size reduction TG, will give an overview of the new Zce extension , explaining the new instructions and showing how they help reduce code size for a wide range of applications. Benchmarking work is seesentionf or the design of Zce. Ibrahim will explain how it was done and will demonstrate how to benchmark your own applications using his analysis script.

Speakers

Tariq Kurd

CPU Architect, Huawei UK

I have over 20 years of CPU archiecture, design and verification, mainly in the embedded space. I've worked on VLIW, multi-threaded, out-of-order cores, security and DSP style cores. I've been at Huawei for 6+ years, and previously was at Broadcom and Nvidia. I'm the chair of the... Read More →

RISCVSummit 2021 Zce Tariq Kurd pdf

Tuesday December 7, 2021 4:00pm - 4:25pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

4:00pm PST

BoF: How RISC-V CPU Design Impacts Performance of Copy Function and Network Speed - Akira Tsukamoto, AIST

(*) What do these kernel patches do for communication networks? (*) Why the performance improves compared to historical copy function (*) The way to optimize software from the book, Computer Architecture: A Quantitative Approach on RISC-V (*) Why the CPU design impacts implementation of software The patches to improve the performance of RISC-V were accepted on June 4th at the Linux Kernel Mailing List. The changes were achieved by optimizing copy functions inside the kernel by mainly reducing the misaligned memory access and pipeline stalls. The knowledge and understanding of the internals of the RISC-V is essential for optimizing hardware level software. The discussion of the optimization took place in the mailing list and forum of RISC-V development board. The RISC-V is the perfect combination of open architecture and open collaboration to improve the industry since it is open ISA and anybody could participate in the public discussions. The talk will also cover how the Computer Architecture knowledge helps to track down the reason and details of improvement in functions of __asm_copy_from-to_user.

Speakers

Akira Tsukamoto

Senior Researcher, AIST (The National Institute of Advanced Industrial Science and Technology Japan)

Akira Tsukamoto works at AIST (The National Institute of Advanced Industrial Science and Technology Japan). His main focusing area is on both software engineering and hardware engineering on network, operating system and system security. He is enthusiastic on any kind of technical... Read More →

2021 12 05 RISC V Summit BOF ucopy AkiraTsukamoto 4 pdf

Tuesday December 7, 2021 4:00pm - 4:55pm PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type Virtual
Presentation Slides Attached Yes

4:30pm PST

Webassembly as Managed Runtime VM in Embedded Systems - Stefan Wallentowitz, Munich University of Applied Sciences

Managed VMs execute application bytecode with strong isolation properties. Smart cards are powered by such managed VMs and browsers have pushed this topic over the last couple of years. Webassembly has become predominant in this field and attracts further use cases. In this talk, Stefan discusses why Webassembly is an interesting technology for embedded systems and current developments. He will drive in security properties and building multi-device trusted systems around the webassembly ecosystem. The talk concludes with an insight about potential RISC-V extensions that could benefit webassembly in embedded systems.

Speakers

Stefan Wallentowitz

Professor, Munich University of Applied Sciences

Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various... Read More →

Tuesday December 7, 2021 4:30pm - 4:55pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual

4:55pm PST

Break

Tuesday December 7, 2021 4:55pm - 5:55pm PST

Breaks

5:30pm PST

Scavenger Hunt Prize Drawing

Complete the Expo Hall Scavenger Hunt card (available in the RISC-V Lounge) during the day, and join us to find out if you win the prize drawing! Must be present to win.

Tuesday December 7, 2021 5:30pm - 5:45pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Expo Hall

8:00am PST

Registration + Vaccine Verification

Wednesday December 8, 2021 8:00am - 5:00pm PST
Level 1 Foyer

Registration

9:00am PST

Lightning Talk: Functional Gap between RISC-V V and SPIR-V: a Study Case on the Graphics Domain - Abel Bernabeu, Esperanto Technologies

The RISC-V V extension opens new possibilities for RISC-V based designs, with big expectations created in the machine learning, heterogeneous computing and graphics communities. In this talk we try to answer the question of what is the functional gap between RISC-V V and the popular SPIR-V standard when handling common graphics use cases. We define the functional gap as the set of SPIR-V instructions that require an unreasonable number of instructions to implement on RISC-V V, but would take just one or two instructions on an ISA specifically designed for graphics. A thorough review of the functional gap is made for a representative study case: using SPIR-V as intermediate representation when translating GLSL shaders from the widely adopted OpenGL ES 2.0 standard to RISC-V V code. The identified functional gap is summarized here for helping the graphics community (represented on the RISC-V Graphics SIG) to familiarize themselves with the areas where work is required.

Speakers

Abel Bernabeu

Senior Engineer, Esperanto Technologies

Abel Bernabeu is a computer scientist with over a decade of experience in the GPU industry, mostly working on software drivers and digital hardware design for companies like Imagination Technologies, ZiiLabs, Intel, Arm and more recently Esperanto Technologies. During his career has... Read More →

Functional Gap between RISC V V and SPIR V pdf

Wednesday December 8, 2021 9:00am - 9:10am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

9:00am PST

RISC-V Enterprise Software Ecosystem Readiness - Kumar Sankaran, Ventana Micro Systems

In this session, we will talk about the RISC-V software eco-system as it pertains to the enterprise and datacenter market segments primarily focused around Linux. Enterprise market segments include storage, networking and control plane while datacenter market segments include web tier, data analytics, social media, databases and such. The session will walk thru the various applications and workloads that are deployed within these market segments and their availability and status for RISC-V. We will take a bottoms-up approach starting with the lowest level of hardware and then working our way up the software stack including the tools, simulators, compilers, firmware, bios, OS, hypervisor, middleware and applications discussing the availability of each of these components within the RISC-V software ecosystem. The session will also provide an overview into the actual porting exercise of what it takes to port an application from upstream to the RISC-V architecture in terms of the steps and typical time taken, with multiple example applications.

Speakers

Kumar Sankaran

VP SW and Solutions, Ventana

Kumar Sankaran heads the Software, Platform Engineering and Solutions Architecture functions for the Ventana high performance RISC-V based CPU solution designed for the Data Center, Edge, Networking, Storage, HPC and Mobile/IoT markets. He plays a key role within RISC-V International... Read More →

Wednesday December 8, 2021 9:00am - 9:25am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type In-person

9:15am PST

Lightning Talk: A Zero Trust Security Architecture For RISC-V SoC/ Platform - Suresh Sugumar, Technology Innovation Institute

Zero Trust (Trust no one, but always verify) has recently become a hot topic in the network security world, where it shifts the paradigm from trust-based on physical connectivity to the one that involves always authenticating every access. The US has also issued an executive order on cybersecurity to embrace Zero Trust not just for networking but also for any products/ services that we build, and semiconductors are at the heart of everything nowadays. In this talk, we shall cover a holistic view of Zero Trust right from the silicon up to software-level security, and how can improve the trust of the platform and every component in it. A platform-level Trusted Execution Environment (TEE) design with configurable and dynamic Trusted Computing Base (TCB) will be explored. A platform-level Root-of-Trust (RoT) to facilitate authentication, encryption of data exchanged between every component, and platform-wide remote attestation to verify the firmware integrity of every component in the platform will be discussed. Also, topics related to supply chain security and trusted foundry will be discussed.

Speakers

Suresh Sugumar

Executive Director, Technology Innovation Institute

A seasoned security architect/ researcher with vast experience on SoCs/ CPUs, currently leading an R&D team at Technology Innovation Institute in Abu Dhabi.

RISC V Summit Zero Trust pdf

Wednesday December 8, 2021 9:15am - 9:25am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

9:30am PST

Esperanto’s Custom RISC-V ISA Extensions for Energy-Efficient Machine Learning Applications - Jayesh Iyer, Esperanto Technologies

Jayesh Iyer, Principal Architect at Esperanto, will explain the development of the company’s custom vector/tensor extensions to the RISC-V instruction-set architecture and how these new instructions are used to implement machine-learning models for data center inferencing applications.

Attendees will learn how the extensions were selected and implemented in the company’s ET-Minion cores, what operations and data types are supported, how the extensions interact with other elements of the chip such as caches and the on-die interconnect, and how developers will be able to take advantage of the high computation and communication bandwidth delivered by Esperanto’s ET-SoC-1 “supercomputer on a chip.”

What attendees will learn:
• How Esperanto designed custom instruction-set extensions to adapt the company’s ET-Minion RISC-V core for machine-learning applications
• How developers can take advantage of these instructions and other chip-level optimizations to achieve high throughput and efficiency for these workloads

This presentation will provide actionable insight into the process of developing and using custom instruction-set extensions for RISC-V processor cores.

Speakers

Jayesh Iyer

Principal Architect, Esperanto Technologies

Jayesh Iyer Is a Principal Architect at Esperanto, and one of its early employees, responsible for architectural definition and performance analysis of the SOC. Prior to that, he was at Intel labs for 13 years working on advanced CPU architectures including HW/SW co-designed microprocessors... Read More →

Wednesday December 8, 2021 9:30am - 9:55am PST
Room 3004/3006

Beyond the RISC-V ISA

Talk Type In-person

9:30am PST

Radiation Hardening and Fault-Tolerance Features of the NOEL-V RISC-V Processor - Jan Andersson, CAES Space System Division, Gaisler

NOEL-V is a is a RISC-V processor model that can be implemented in various configurations ranging from RV32I to RCV64GC. The NOEL-V processor has been developed by the CAES Gaisler Products group that has a long heritage of supplying processor implementations, both as IP cores and as ready-made radiation-tolerant standard products, for space applications. Jan Andersson will provide an overview of the fault-tolerance features implemented in the NOEL-V processor core and a description of the first radiation-hardened testchip. The presentation will describe how hardening measures against radiation effects is tied to different target technologies (for example ASIC vs. FPGA) and will also provide an overview of the GR7xV development, which is a 16-core RISC-V based processor targeted towards space applications.

Speakers

Jan Andersson

Director, Engineering, Cobham Gaisler AB

Mr Jan Andersson M.Sc in Computer Engineering focused on digital design and embedded systems. Working for CAES as Director of Engineering for Gaisler Products, where he oversees hardware and software development efforts and leads implementation of the system-on-chip architecture roadmap... Read More →

RV Summit 2021 RH and FT NOEL V pdf

Wednesday December 8, 2021 9:30am - 9:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

10:00am PST

Break

Wednesday December 8, 2021 10:00am - 10:30am PST
TBA

Breaks

10:00am PST

Expo Hall

Wednesday December 8, 2021 10:00am - 6:00pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Expo Hall

10:05am PST

Demo: RISC-V Software Debug in an Emulation Environment - Andy Meier, Siemens

Software-enabled debug in an emulation-based verification environment is advantageous to designers working on RISC-V-based designs, as opposed to manually traversing static log files and waveforms from simulation. Because the RISC-V community’s needs are so diverse, this debug environment must be capable of managing IP from multiple providers including custom implementation of the RISC-V architecture. This presentation gives you a glimpse at what software-enabled debug options are possible for your RISC-V-based designs.

Speakers

Andy Meier

Product Manager, Siemens

Andy Meier is a product manager in the Scalable Verification Solutions Division at Siemens EDA. He holds a Bachelor of Science degree in Engineering and Computer Engineering from Worcester Polytechnic Institute in Worcester, Mass.

Veloce Codelink DAC final pdf

Wednesday December 8, 2021 10:05am - 10:15am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person
Presentation Slides Attached Yes

10:20am PST

Demo: Software Design: Porting Software to RISC-V using Imperas Virtual Platforms - Katherine (Kat) Hsu & Manny Wright, Imperas Software

While much of the focus and energy of the RISC-V adopters has so far gone into the development of the RISC-V architecture and specific cores, the real success of RISC-V is dependent upon the key software tasks for new applications, porting legacy software, and optimising OS/RTOS ports and drivers for the wide range of

RISC-V devices being built. With more custom silicon projects starting every day, virtual platforms (often called virtual prototypes) offer a viable alternative to hardware prototypes for software engineering tasks.
This talk will highlight how simulation and virtual platforms can be used for software development for new processors and SoCs including a demonstration.

Speakers

Katherine (Kat) Hsu

Senior Account Manager, Imperas Software

Katherine Hsu is a Senior Account Manager with Imperas Software. Kat is a multi-disciplinary expert in embedded systems simulation and end-to-end cybersecurity. She has a track record of introducing and deploying advanced technologies for global enterprise customers. Prior to Imperas... Read More →

Man Wai (Manny) Wright

Sr. Consulting Engineer, Imperas Software

Imperas RISC V Theater Demo (Kat Hsu) Quake on RISC V Demo RISC V Summit 2021 pdf

Wednesday December 8, 2021 10:20am - 10:30am PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person
Presentation Slides Attached Yes

10:30am PST

Lightning Talk: Adding H Support to the NOEL-V Microprocessor - Stefano Ribes, De-RISC Project

As part of the Dependable Real-Time Infrastructure for Safety Critical Computer (De-RISC) project, the open-source NOEL-V RV64GC processor has been extended to support the Hypervisor (H) extension of the RISC-V ISA. The talk will describe the engineering effort involved to implement the H extension and the resulting impact on parameters such as implementation complexity.

Speakers

Stefano Ribes

Design Engineer, Cobham Gaisler AB

Stefano Ribes, Licentiate of Technology in Computer Engineering, Working for CAES Space Division, Gaisler products and part of the De-RISC project. Stefano's experience is in digital design with a focus on AI accelators and High Level Synthesis.

CAES H Support NOEL V pdf

Wednesday December 8, 2021 10:30am - 10:40am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

10:30am PST

Quantitative Methods for Continuously Improving RISC-V Compilers - Philipp Tomsich, VRULL

Up until now, most commercial implementations of RISC-V have focused on embedded use cases; with the emergence of RISC-V as an alternative to the ARM and Intel ecosystems, higher-end applications that include storage and the datacenter are moving into focus. This also shifts the perspective on target workloads and representative benchmarks. We show how quantitative methods can be used to assess the quality of code generation and identify and prioritize potential improvements based on hot-block analysis, dynamic instruction count metrics, and instruction histograms. The difference applicability to small benchmarks (such as Coremark, where this method identifies both a superoptimisation opportunity for the CRC functions and highlights the absence of conditional-move instructions in the RISC-V instructions set) and large benchmarks (such as SPEC, which helps to improve and mature the tools across the board) are demonstrated. The proposed methodology can provide much-needed quantitative data to the standardization of new extensions, guide future micro-architecture development and provide quality-metrics for toolchain development.

Speakers

Philipp Tomsich

Chief Technologist, VRULL GmbH

Wednesday December 8, 2021 10:30am - 10:55am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type In-person

10:45am PST

Lightning Talk: A Secure RISC-V Based SoC for Autonomous UAVs Navigation - Davide Rossi, University of Bologna & Daniele Palossi, IDSIA USI-SUPSI Lugano

Advanced computing platforms for autonomous drone navigation are extremely challenging drivers of Internet-of-Things edge intelligence capabilities due to the mix of requirements in terms of security, safety and high performance. We present a fully RISC-V-based SoC for high-performance and secure autonomous drone navigation. The SoC includes a dual-core CVA6 core with full support for Linux OS managing the main system functions and an RTOS such as Nuttx for time-critical tasks. The SoC is supported by a complete set of peripherals, and a parallel accelerator based on the open-source PULP platform and a root-of-trust subsystem based on the open titan project. As a capability demonstrator, we present a human pose estimation task based on a novel CNN. Inference runs in real-time, up to 135 frame/s, consuming less than 87 mW on a COTS PULP-based SoC aboard a 27-grams nano-UAV, where it achieves 1 GOPS with an efficiency of more than 12 GOPS/W. The in-field deployment of our visual NN demonstrates a closed-loop top-notch autonomous navigation capability. Our novel RISC-V-based SoC is expected to push this cutting-edge end-to performance even further, as much as 2.6 GOPS and 92 GOPS/W.

Speakers

Davide Rossi

Prof., university of Bologna

Davide Rossi, received the PhD from the University of Bologna, Italy, in 2012 where he currently holds an associate professor position. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems... Read More →

Daniele Palossi

Dr., IDSIA USI-SUPSI Lugano

Daniele Palossi received the Ph.D. in Information Technology and Electrical Engineering from the ETH Zürich, in 2019. He is currently a Postdoctoral Researcher at the Dalle Molle Institute for Artificial Intelligence (IDSIA), USI-SUPSI, Lugano, Switzerland, and at the Integrated... Read More →

D ROSSI RISC V SUMMIT pdf

Wednesday December 8, 2021 10:45am - 10:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

11:00am PST

Lightning Talk: Performance of TVM AutoScheduler for Andes Vector Processor - I-Wei Wu, Andes Technology

Apache TVM is an open source machine learning compiler framework which supports several CPUs and GPUs. To optimize diversified machine learning applications on various hardware platforms, TVM recently introduced AutoScheduler that explores many optimization strategies and then identify the best one using evolutionary algorithm. In this talk, the compilation flow of TVM and AutoScheduler is introduced first. Then, several enhancements used to enable AutoScheduler on a platform with Andes vector processor NX27V with RISC-V RVV Extension are also explained. To demonstrate the power of AutoScheduler on Andes NX27V platform, we will go through some experiments with AutoScheduler and compare their results with those from hand-optimized code.

Speakers

Alec Wu

Manager of Toolchain Group, Andes Technology

I-Wei Wu is a manager at Andes technology, leading toolchain group to develop assembler, linker, COPILOT and AI compiler. He received the B. S. and the M. S. degree in Electronics Engineering from Feng Chia University (Taiwan) in June 200 and June 2002 respectively, and the Ph.D... Read More →

Wednesday December 8, 2021 11:00am - 11:10am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type Virtual

11:00am PST

Unveiling the SweRV Core EH3 - Zvonimir Bandic, Western Digital

Western Digital has introduced a family of leading RISC-V cores branded as the SweRV Cores. The existing architectures offer the RISC-V community leading performance and power for embedded applications. With the unveiling of the SweRV EH3 core Western Digital embarks on a new trajectory. Learn about the higher performance capabilities, architectural details and timeline. During the technical talk we will discuss how to partner with Western Digital for SweRV EH3 access.

Speakers

Zvonimir Bandic

Senior Director, Western Digital

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and... Read More →

ehx3 open noNDA Nov 18 2021 rev8b pdf

Wednesday December 8, 2021 11:00am - 11:25am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person
Presentation Slides Attached Yes

11:15am PST

Lightning Talk: Bring Multicore RISC-V and Zephyr RTOS Together - Chun-Wei Shu, Andes Technology

Zephyr RTOS is an Open Source RTOS with multicore support like SMP and AMP. Currently, Zephyr SMP feature doesn't support RISC-V arch. To enable Zephyr RTOS on Andes RISC-V SMP processors, Chun-Wei have ported RISC-V SMP support of Zephyr. In this talk, Chun-Wei would like to share the experiences of the architecture porting of SMP kernel. It contains how to integrate RISC-V HW to Zephyr SMP kernel and general SMP programming concept used in the kernel porting.

Speakers

Chun-Wei Shu

Advanced Software Engineer, Andes Technology

I'm a software engineer from Andes Technology. I have 3 year working experience on RTOS and firmware development. Mainly focus on the architectural (RISC-V, NDS32) porting, kernel feature / middleware support, and driver development in my job. Most experienced programming language... Read More →

Wednesday December 8, 2021 11:15am - 11:25am PST
Room 3004/3006

Software Stack Integration and Development Tools

Talk Type Virtual

11:30am PST

Profiles and Platforms - Philipp Tomsich, VRULL & Mark Himelstein, RISC-V International

We are always asked how we will stop fragmentation amongst RISC-V. members. The incentive to not fragment is to reduce duplicated effort and share work in the software ecosystem. The "how" is answered by Profiles and Platforms. New to 2021 these standards provide a single group of extensions and OS components that enable us to tell developers and distros alike what to target for upstream projects from boot code to hypervisors, operating systems, applications and tool chains. Come learn about these standards and how they unify the RISC-V community.

Speakers

Mark Himelstein

CTO, RISC-V International

Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management... Read More →

Philipp Tomsich

Chief Technologist, VRULL GmbH

Wednesday December 8, 2021 11:30am - 11:55am PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person

11:30am PST

A Requirements-based Test Suite for the C Standard Library: SuperGuard - Marcel Beemster, Solid Sands B.V.

Solid Sands has developed a requirement-based test suite for the C standard library, with traceability from individual test results to the requirements derived from the ISO C language specification. It is called SuperGuard and can be used to qualify C library implementations for safety-critical applications.

The ISO C specification is not a list of requirements. From it we distilled the requirements on the C library. This was a huge effort, but required for library qualification. Next we created test specifications and matched them with our existing test suite. Finally, tools were created to drive the test suite and report the test results so that they are fully traceable to the requirements and the specification.

The C library is not insensitive to the application's compilation options: many functions are implemented as macros defined in header files. Functional Safety standards clearly specify that qualification must be done for the application developer’s use-case, so this is what we make possible with SuperGuard.

In this presentation we will show the principles and practice of C standard library qualification.

Speakers

Marcel Beemster

CTO, Solid Sands B.V.

Before starting Solid Sands, I was an assistant professor at the University of Amsterdam and later switched to the industry as a compiler developer at ACE Associated Compiler Experts. I love the C programming language, right from the first day I picked up K&R’s book, because it... Read More →

BeemsterSuperGuardLibcVerification pdf

Wednesday December 8, 2021 11:30am - 11:55am PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

12:00pm PST

Lunch Break (Attendees on Own)

Wednesday December 8, 2021 12:00pm - 1:30pm PST
TBA

Breaks

1:30pm PST

Keynote: Road Ahead - Mark Himelstein, CTO, RISC-V International

Speakers

Mark Himelstein

CTO, RISC-V International

Wednesday December 8, 2021 1:30pm - 1:45pm PST
Room 3008 - 3012

Keynote Sessions

1:50pm PST

Keynote: Is Hardware/software Co-design for Applications Now a Reality with RISC-V? - Kevin McDermott, Vice President Marketing, Imperas Software Ltd

RISC-V Vector instructions offer significant flexibility and options to configure a hardware accelerator for applications such as Datacenters and AI. Following initial cloud-based development with extensive real-world datasets, the migration to a hardware accelerator array with RISC-V vectors is redefining the software driven approach to hardware design.

This talk highlights SoC architectural exploration with multicore arrays and optimized RISC‑V processors to support early software development for vector accelerators. It introduces some of the challenges and discusses different approaches being adopted in the community/industry.

Speakers

Kevin McDermott

Vice President Marketing, Imperas Software Ltd

Imperas Keynote Talk (McDermott) Virtual Prototypes for RISC V RISC V Summit 2021 pdf

Wednesday December 8, 2021 1:50pm - 2:00pm PST
Room 3008 - 3012

Keynote Sessions

Presentation Slides Attached Yes

2:00pm PST

Keynote: Awards Presentation - Kim McMahon, Director of Visibility & Community Engagement, RISC-V International & Mark Himelstein, CTO, RISC-V International

Speakers

Mark Himelstein

CTO, RISC-V International

Kim McMahon

Director of Visibility & Community Engagement, RISC-V International

Wednesday December 8, 2021 2:00pm - 2:10pm PST
Room 3008 - 3012

Keynote Sessions

2:15pm PST

Keynote: Scaling is Failing - Dr. Ron Black, CEO, Codasip

After 50 years of driving semiconductor economics, the underlying “semiconductor laws” are failing at a time when advanced manufacturing is becoming prohibitively expensive. Photonics and alternate materials such as carbon nanotubes have been suggested as alternatives but the only short-term option is to match hardware to computational workload through heterogeneous computing. RISC-V’s modularity combined with design automation provides a foundation for creating novel processors and domain-specific accelerators. Industry must adapt or die!

Speakers

Dr. Ron Black

CEO, Codasip

30 years in semiconductors and electronics systems. Previous roles as CEO since 2005• CEO of Wavecom: sold to Sierra Wireless• CEO of Mobiwire, sold to TCL• President and CEO of Rambus,• President and CEO of Imagination Technologies• CEO of Codasip

Wednesday December 8, 2021 2:15pm - 2:25pm PST
Room 3008 - 3012

Keynote Sessions

2:30pm PST

Keynote: The Showcase of RISC-V Wins!

Wednesday December 8, 2021 2:30pm - 2:35pm PST
Room 3008 - 3012

Keynote Sessions

2:40pm PST

Keynote: Where is RISC-V Going? - Calista Redmond, CEO, RISC-V International

Speakers

Calista Redmond

CEO, RISC-V International

Wednesday December 8, 2021 2:40pm - 3:00pm PST
Room 3008 - 3012

Keynote Sessions

3:00pm PST

Break

Wednesday December 8, 2021 3:00pm - 3:30pm PST
TBA

Breaks

3:05pm PST

Demo: Processor Trace: Efficient Solutions for Today’s SoCs - Hanan Moller, Siemens EDA

RISC-V is being used in complex real-time heterogeneous systems. The software executing on such systems needs to be tuned to provide the best performance possible. Developers need insight into the operation of the software and its interaction with the underlying hardware structures, including NoCs and CPUs. A key element of this is processor trace, which allows development teams to analyze program execution, how many cycles code takes to execute, whether there are stalls and dependencies and how long they last. System designers can use these insights to make optimizations and achieve efficiency gains.

The Efficient Trace for RISC-V (E-Trace) specification supports these needs.
This presentation will outline the latest developments in E-Trace, and provide details of the features of the Embedded Analytics RISC-V Trace encoder, which implements features such as cycle-accurate and data trace, filtering, matching and SoC-wide cross-triggering, that can be used to produce significant improvements in overall system performance.

Speakers

Hanan Moller

Technical Director, Application Engineering, Siemens EDA

Wednesday December 8, 2021 3:05pm - 3:15pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type In-person

3:20pm PST

Demo: Debian Linux at octacore SCR7-based SDK - Sergey Yakushkin, Syntacore

We’ll demonstrate SCR7-based SDK, running Debian Linux. System is based on the standard of-the-shelf available FPGA board and contains multicore SCR7 in SMP configuration as well as system environment, including DDR, Gigabit Ethernet, PCI-based storage and low-speed peripherals. We boot Debian Linux and demonstrate different tests and benchmarks, running on the platform.

Speakers

Sergey Yakushkin

Director of SW Engineering, Syntacore

Director of software engineering at Syntacore, company developing microprocessor IP based on RISC-V architecture and co-founder of RISC-V International. I have 15+ years of experience in compilers, code-generation and optimizations for novel ISA and processor micro-architectures... Read More →

Demo Debian Linux at octacore SCR7 based SDK pdf

Wednesday December 8, 2021 3:20pm - 3:30pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Demo Theater

Talk Type Virtual
Presentation Slides Attached Yes

3:30pm PST

Systematically Securing the RISCV - Secure Foundation for Embedded Functionality - Marko Mitic, NVIDIA

Drawing inspiration from the academic/industry work around Multiple Independent Levels of Security and Safety (MILS), NVRISCV/Peregrine security architecture is presented that offers multiple isolated execution environments - partitions, all running on the same physical processor with SW defined and HW enforced capabilities. NVRISCV is NVIDIA’s implementation of the RISC-V ISA and Peregrine subsystem includes NVRISCV and multiple peripherals. They show how fine-grain access controls, formally verified for correctness, allow following the principle of least privilege for each partition. NVRISCV provides secure boot that starts with an immutable HW, the chain of trust extends to the Secure Monitor in SW, where partition policies are set up and isolation enforced using HW controls. Boot and Secure Monitor software is implemented in SPARK, formally verifiable programming language with verification toolset. Holistic approach on HW/SW security must consider attacks outside of defined architecture. The HW is hardened against in-field attacks, via multiple countermeasures they present in detail as well as the offensive research analysis against the architecture.

Speakers

Marko Mitic

Software Security Architect, NVIDIA

Marko is a Software Security Architect focused on secure system design and product security. For the past 8 years at NVIDIA he worked on designing key security aspects for the core system software architecture and drove offensive security practices for GPU system software. He was... Read More →

RISCV Summit 2021 NVIDIA pdf

Wednesday December 8, 2021 3:30pm - 3:55pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type In-person

3:30pm PST

TEEP (Trusted Execution Environment Provisioning) and Software Updates for Internet of Things (SUIT) on RISC-V - Akira Tsukamoto, AIST

The presentation is about the security technology to expand the are of RISC-V on the devices that require security sensitive software and data, IoT/Edge/Network/Automotive equiments. IETF is engineering and standardizing the TEEP (Trusted Execution Environment Provisioning) protocol and (SUIT) Software Updates for Internet of Things. The TEEP is to remotely install/update a TC (Trusted Component, which was previously called Trusted Application) and SUIT manifest is a format to bundle of metadata about code/data of the TC. The implementation started only on Arm and Intel, thus we have developed TEEP and SUIT on RISC-V. TEEP handshakes between TAM(Trusted Application Manager) and the Devices while installing and updating the TC with code signing and certificates based PKI key technology. The TC would be firmware, applications and/or personal data of the Devices to installation or updates. The formats of TEEP and SUIT are encoded and decoded with CBOR (Concise Binary Object Representation) which has the benefit for small binary size to suit on resource constrained embedded devices. The presentation will also include instruction of basic concepts and design of TEEP and SUIT.

Speakers

Akira Tsukamoto

Senior Researcher, AIST (The National Institute of Advanced Industrial Science and Technology Japan)

2021 12 04 RISC V Summit TEEP 2 pdf

Wednesday December 8, 2021 3:30pm - 3:55pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

4:00pm PST

Lightning Talk: Enabling RISC-V Software Ecosystem with VisionFive - an Affordable and Open Source RISC-V Single Board Development Platform with Support for Fedora - Chin Hu Ong, StarFive Technology

VisionFive is the first affordable and Linux capable RISC-V single board development platform using StarFive JH7100 vision processing chip. Based on the RISC-V architecture, VisionFive pushes open-source to the next level and gives developers & RISC-V ecosystem more freedom and capability to innovate and develop industry-leading solutions. VisionFive is powered by SiFive U74 Dual-Core 64-bit RV64GC cores running at 1.5GHz with 4GB/8GB LPDDR4 RAM variants and has rich I/O peripherals such as USB 3.0 ports, 40 pin GPIO header, Gigabit Ethernet Connector, Micro-SD card slot and much more. VisionFive also has rich AI features with StarFive Neural Network Engine and NVDLA Engine. It has onboard audio and video processing capabilities and has MIPI-CSI and MIPI-DSI connectors for video hardware. It has wireless capabilities with Wi-Fi and Bluetooth (BLE) and has a wide software compatibility including support for Fedora.

Speakers

Chin Hu Ong

VP, StarFive Technology

Ong Chin Hu has >20 years of industry experiences in leading SoC and IP solutions roadmap & development for RISC-V and ARM-based SoC product. Currently, Chin Hu is the VP of StarFive Technology, leading Malaysia Design Center focusing on developing differentiated IPs & Subsystems... Read More →

VisionFive single board development platform ChinHuOng pdf

Wednesday December 8, 2021 4:00pm - 4:10pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

4:00pm PST

IOPMP Updates: The Protection of IOPMP - Paul Shan-Chyun Ku, Andes Technology

Platform security is an investable issue nowadays. One fundamental requirement is memory isolation. Inside a RISC-V core, PMP creates isolated spaces. In a platform, IOPMPs do it for the other bus masters. However, the system becomes vulnerable if the malicious code manipulates an IOPMP and allows illegal access. Thus, IOPMPs should also be protected. Unlike PMP, IOPMP has no corresponding CSRs whose access right is constraint by processor modes. IOPMP should recognize the legal control operations first, that is, those accesses from the security monitor. Furthermore, IOPMPs should be able to protect some sensitive data even when the security monitor is breached. A dedicated IOPMP can be used to bridge the MMIO bus and all bus masters, and at the same time to block out illegal control operations to the rest of IOPMPs as well as itself as a way of protection. Such a way controls the operations in a grain of as fine as 4 bytes. When we only want to lock several bits in a control register, e.g., enforce a certain source id to associate with a specific memory domain, we need a fine-grained lock mechanism. In this talk, we will also present these approaches to protect IOPMPs.

Speakers

Paul Ku

Deputy Technical Director, Andes Technology

Dr. Ku is working for Andes Technology Corporation and is enthusiastic about processor and platform security. Besides, in RISC-V International Association, he serves the TEE Task Group as the vice-chair and is currently focusing on the IOPMP proposal. He ever worked for Faraday Technology... Read More →

IOPMP Updates Protection of IOPMP Andes Technology pdf

Wednesday December 8, 2021 4:00pm - 4:25pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

4:15pm PST

Lightning Talk: First Volume Production RISC-V Silicon/SOC to Provide Complete Personal Computing Platform Solution Targeting Mid-range and Edge Computing - Johnson Sun, StarFive

JH7110 will be the first volume production RISC-V Silicon/SOC to provide complete personal computing platform solution targeting mid-range and edge computing. It has a four-core RISC-V cluster which provides the highest performance in the RISC-V personal computing platofrm in the market. The SOC also included other computing components such as GPU, ISP, encoder, decoder, etc. In addition, its PCIE interface provides very flexible expansion to allow various system design and differentiation. Plus, its dual display up to 4K30fps will provide a wide range of systems application such as notebooks and desktop computing with multiple display as a standard.There are a lot of challenges during the developement and verification to reach high volume quality and we like to share what we have ran into and what we learned and how we solved the issues.

Speakers

Johnson Sun

Senior director, StarFive Technology

Johnson Sun, direcotor of StarFive Technology.He lead and manage soc department at Starfive, and experienced in SOC agile design flow, architecture design,chip development planning and management. Under the leadship of Johnson Sun,SOC team developed 4 chips in two years,and his team... Read More →

First volume production RISC V SOC Johnson.Sun pdf

Wednesday December 8, 2021 4:15pm - 4:25pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual
Presentation Slides Attached Yes

4:30pm PST

Architecture Design for Security: Do’s and Don’ts - Gregory T. Sullivan, Dover Microsystems, Inc.

Having ported Dover Microsystems’ CoreGuard security product to several architectures, including RISC-V, we have some lessons learned about how well-intentioned features can make the task of implementing reliable, fine-grained security gratuitously difficult. While some of our talk will focus on subtle instruction set design tradeoffs, we also have a larger, more urgent message to convey to the RISC-V community about designing an architecture that is friendly to future, innovative security products. A non-exhaustive list of gotchas from RISC-V and other ISAs: (1) exception delegation, where was EPC stored? (2) multi-word load/stores operations paused or canceled due to interrupt or exception - what loads/stores were executed; also when are we resuming? (3) lazy register spills - too clever by half! (4) punning JAL for exception return - saves max 2 instructions, adds complexity. (4) register windows and wraparound - complexity better handled in compiler than HW. We strongly encourage a general, trace-based introspection feature to support a wide range of debugging and security products, rather than per-feature-ISA extensions that will eventually throttle the ISA due to complexity.

Speakers

Greg Sullivan

Chief Scientist, Dover Microsystems

Greg Sullivan is Chief Scientist and co-founder of Dover Microsystems. At Dover, Greg helps communicate technical concepts both internally and to customers, and contributes to design and implementation of the CoreGuard product. Earlier, Greg worked at Draper laboratory, which led... Read More →

Dover SecureDesignV3Pruned pdf

Wednesday December 8, 2021 4:30pm - 4:55pm PST
Room 3005/3007

Beyond the RISC-V ISA

Talk Type Virtual
Presentation Slides Attached Yes

4:30pm PST

Storage Area Network Acceleration using RDMA / RoCE and RISC-V - Pu Wang, DatenLord

In this talk, we will introduce an SoC for storage area network (SAN) acceleration. As for SAN, RDMA over Converged Ethernet (RoCE) is the mainstream solution, since its performance is close to InfiniBand and avoids special InfiniBand equipment by reusing existing Ethernet. However, the most weakness of RoCE is the flow control. RoCE depends on the flow control to prevent the underlying Ethernet from packet loss. Whereas Ethernet itself is not lossless in nature. There have been many flow control algorithms proposed for RoCE, such as HPCC, DCQCN, TIMELY, etc. But all require complex and manual parameter tuning. We build an SAN acceleration SoC by combining RoCE and RISC-V, that the RoCE protocol is implemented in hardware and the RoCE flow control algorithms are implemented as software to run in RISC-V. By doing so, we achieve both hardware acceleration for RoCE and flexibility for flow control parameter tuning, which exactly follows hardware and software co-design philosophy. Further, we leverage AI techniques to automatically tune the flow control parameters, which greatly reduces the burden of manual tuning and achieves significently better performance than the manual way.

Speakers

Pu Wang

Co-founder, DatenLord

Dr. Pu Wang is the co-founder of the DatenLord project, which is a Geo-distributed storage system by leveraging software and hardware co-design to achieve high performance. Dr. Wang used to work at Google. He was in charge of large scale Ads related user data management, especially... Read More →

Wednesday December 8, 2021 4:30pm - 4:55pm PST
Room 3004/3006

Industry Targeted Solutions

Talk Type Virtual

4:55pm PST

Break

Wednesday December 8, 2021 4:55pm - 5:55pm PST
TBA

Breaks

5:30pm PST

Scavenger Hunt Prize Drawing

Complete the Expo Hall Scavenger Hunt card (available in the RISC-V Lounge) during the day, and join us to find out if you win the prize drawing! Must be present to win.

Wednesday December 8, 2021 5:30pm - 5:45pm PST
Exhibit Hall - 2nd Floor - RISC-V Demo Theater

Expo Hall