David is a System Architect at Ventana Micro Systems, responsible primarily for the specification of the cache and memory subsystem architecture and the specification of other system-level functionality and requirements pertaining to Ventana's IP. His previous experience includes circuit design, RTL coding, and architecture specification of TLBs and caches, and he has architected several commercially successful cache coherence protocols, including one implemented in a widely-used cache-coherent interconnect IP and another implemented in multiple generations of an ARM-based server SoC. He is also currently the chair of the Cache Management Operations (CMO) task group.