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December 6-8, 2021 | San Fransisco, CA + Virtual
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Jérôme Quévremont

Thales
RISC-V and open hardware project leader
France

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Jérôme Quévremont is RISC-V and open hardware project leader at Thales Research and Technology (TRT), Palaiseau, France. He serves as the chair of the OpenHW Group Technical WG and the technical leader of the CVA6 (formerly ARIANE) application core project. He is also the chairman of the Functional Safety special interest group at RISC-V International. His past experience includes the development of telecom and security integrated circuits at Texas Instruments and Thales Communications then the management of a development lab specialized in secure- and crypto-chips, mostly in ASIC technologies. He joined TRT in 2020.
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