RISC-V Summit has ended
December 6-8, 2021 | San Fransisco, CA + Virtual
Learn More & Register Now

avatar for Jérôme Quévremont

Jérôme Quévremont

RISC-V and open hardware project leader

Contact Me

Jérôme Quévremont is RISC-V and open hardware project leader at Thales Research and Technology (TRT), Palaiseau, France. He serves as the chair of the OpenHW Group Technical WG and the technical leader of the CVA6 (formerly ARIANE) application core project. He is also the chairman of the Functional Safety special interest group at RISC-V International. His past experience includes the development of telecom and security integrated circuits at Texas Instruments and Thales Communications then the management of a development lab specialized in secure- and crypto-chips, mostly in ASIC technologies. He joined TRT in 2020.
  • Timezone
  • Filter By Date RISC-V Summit Dec 6 - 8, 2021
  • Filter By Venue San Fransisco, CA
  • Filter By Type
  • Beyond the RISC-V ISA
  • Breaks
  • Demo Theater
  • Expo Hall
  • Industry Targeted Solutions
  • Keynote Sessions
  • Registration
  • Software Stack Integration and Development Tools
  • Talk Type
  • Presentation Slides Attached