Cui Jin is working as a principal engineer in architecture team of StarFive, working on RISC-V SoC micro-architecture modelling and simulation. Before joining StarFive, he has more than 10 year industrial experience, working as a principal engineer in Huawei Singapore Research Centre and as a staff engineer in Intel Mobile Communications Singapore after obtaining PhD from Nanyang Technological University in 2012. His expertise is on both computing micro-architecture and embedded software development, including hypervisor(virtualization), OS kernel, driver/firmware, compiler, EDA tools(placement and routing algorithm), CPU/FPGA architecture modelling, simulation, exploration and performance profiling & optimization. He participated and played critical roles in some industrial project developments, including mobile SoC, baseband chip, DSP/FPGA architecture design in both Intel and Huawei.