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December 6-8, 2021 | San Fransisco, CA + Virtual
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avatar for Sébastien Jacq

Sébastien Jacq

Thales
Research engineer
Sébastien Jacq is research engineer at Thales Research and Technology. He specializes in the design of digital computational architecture and in the implementation of algorithms on FPGA / SoC / MPSoC target. Sébastien is currently an actor in the RISC-V community. He actively contributes to the development of the CVA6 processor of the OpenHW group. Especially, he added Linux support to the 32-bit flavor of CVA6. Sébastien is now working on the optimization of CVA6 for FPGA targets.
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