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RISC-V Summit has ended
December 6-8, 2021 | San Fransisco, CA + Virtual
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avatar for Sergey Yakushkin

Sergey Yakushkin

Syntacore
Director of SW Engineering
St. Petersburg
Director of software engineering at Syntacore, company developing microprocessor IP based on RISC-V architecture and co-founder of RISC-V International. I have 15+ years of experience in compilers, code-generation and optimizations for novel ISA and processor micro-architectures, development of debugging, profiling and simulation tools, design of domain-specific and architecture description languages for co-design. Worked at academia and industry including Intel, RWTH, Huawei, Synopsys, published papers and talks at international conferences such as LLVM, DATE, DAC, HPCA.
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