RISC-V Summit has ended

Create Your Own Event

RISC-V Summit

December 6-8, 2021 | San Fransisco, CA + Virtual
Learn More & Register Now

9:00am PST

A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India Room 3005/3007

9:30am PST

Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications - Shubu Mukherjee, SiFive Room 3005/3007

10:30am PST

Open Hardware for the Open Cloud - Daniel Mangum, Upbound Room 3005/3007

11:00am PST

Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services Room 3005/3007

11:30am PST

Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC Room 3005/3007

3:30pm PST

YoC, an Open Operation System for IoT - Vincent Cui, Alibaba Room 3005/3007

4:00pm PST

Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA Room 3005/3007

4:30pm PST

Advanced Interrupt Architecture and Advanced CLINT - Anup Patel, Western Digital & John Hauser, Independent Researcher Room 3005/3007

9:00am PST

Support for Non-Coherent I/O Devices in RISC-V - Greg Favor & David Kruckemyer, Ventana Micro Systems Room 3005/3007

9:30am PST

Continuous Innovation in Embedded RISC-V Processors - Drew Barbier, SiFive Room 3005/3007

10:30am PST

RISC-V Compatible Processor IP by Syntacore: Compact Open-source MCU to Multicore Linux - John Hartley, Syntacore Room 3005/3007

11:00am PST

Lightning Talk: RISQV-HT: A RISC-V Microcontroller Delivering Post-Quantum Secure Encryption - and Hardware Trojans - Alexander Hepp, Technical University of Munich Room 3005/3007

11:15am PST

Lightning Talk: Enabling Software Emulation for RISC-V Heterogeneous Cores Architecture - Cui Jin & Ley Foon Tan, StarFive Technology Room 3005/3007

11:30am PST

RISC-V Debug in the OS-A Platform - Paul Donahue, Ventana Micro Systems Room 3005/3007

3:30pm PST

AI-RISC - Custom Extensions to RISC-V for Energy-efficient AI Inference at the Edge of IoT - Vaibhav Verma, University of Virginia Room 3005/3007

4:00pm PST

Exploring the Zce Code-size Reduction ISA Extension - Tariq Kurd, Huawei UK Room 3005/3007

4:30pm PST

Webassembly as Managed Runtime VM in Embedded Systems - Stefan Wallentowitz, Munich University of Applied Sciences Room 3005/3007

9:00am PST

Lightning Talk: Functional Gap between RISC-V V and SPIR-V: a Study Case on the Graphics Domain - Abel Bernabeu, Esperanto Technologies Room 3005/3007

9:15am PST

Lightning Talk: A Zero Trust Security Architecture For RISC-V SoC/ Platform - Suresh Sugumar, Technology Innovation Institute Room 3005/3007

9:30am PST

Radiation Hardening and Fault-Tolerance Features of the NOEL-V RISC-V Processor - Jan Andersson, CAES Space System Division, Gaisler Room 3005/3007

10:30am PST

Lightning Talk: Adding H Support to the NOEL-V Microprocessor - Stefano Ribes, De-RISC Project Room 3005/3007

10:45am PST

Lightning Talk: A Secure RISC-V Based SoC for Autonomous UAVs Navigation - Davide Rossi, University of Bologna & Daniele Palossi, IDSIA USI-SUPSI Lugano Room 3005/3007

11:00am PST

Unveiling the SweRV Core EH3 - Zvonimir Bandic, Western Digital Room 3005/3007

11:30am PST

Profiles and Platforms - Philipp Tomsich, VRULL & Mark Himelstein, RISC-V International Room 3005/3007

3:30pm PST

Systematically Securing the RISCV - Secure Foundation for Embedded Functionality - Marko Mitic, NVIDIA Room 3005/3007

4:00pm PST

IOPMP Updates: The Protection of IOPMP - Paul Shan-Chyun Ku, Andes Technology Room 3005/3007

4:30pm PST

Architecture Design for Security: Do’s and Don’ts - Gregory T. Sullivan, Dover Microsystems, Inc. Room 3005/3007