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9:00am • XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)
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9:30am • Lightning Talk: Improving Performance of National Crypto Algorithms with Custom Instructions - Alexander Kozlov, CloudBEAR
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9:45am • Lightning Talk: A System Level Verification and Validation Environment using SweRV - Anupam Bakshi, Agnisys, Inc.
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10:30am • Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar, TU Dresden & Dr. William Jones, Embecosm
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10:45am • Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software
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11:00am • Lightning Talk: De-RISC, the Horizon 2020 Project that will Create the First RISC-V, Fully European Platform for Aerospace - Paco Gómez-Molinero, fentISS
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11:15am • Lightning Talk: Adding 32-bit Linux Support to ARIANE/CVA6 Open-source Application Core - Sébastien Jacq & Jérôme Quévremont, Thales
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11:30am • Extending RISC-V Instructions for 5G Intelligent RAN Base Stations - Gururaj Padaki & Sriram Rajagopal, EdgeQ
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3:30pm • RISC-V on Edge: Porting EVE and Alpine Linux to RISC-V - Roman Shaposhnik & Kathy Giori, ZEDEDA Inc.
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4:00pm • Lightning Talk: Accelerating Real-World AI Software using the RISC-V Vector Extension - Colin Davidson & Alastair Murray, Codeplay Software
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4:15pm • Lightning Talk: Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks - David Luo, Mythic & Dr Zdeněk Přikryl, Codasip
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4:30pm • Hard Real-Time vs High Performance Real-Time Applications on PolarFire SoC - Hugh Breslin, Microchip Technology
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9:00am • A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India
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9:30am • Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications - Shubu Mukherjee, SiFive
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10:30am • Open Hardware for the Open Cloud - Daniel Mangum, Upbound
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11:00am • Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services
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11:30am • Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC
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3:30pm • YoC, an Open Operation System for IoT - Vincent Cui, Alibaba
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4:00pm • Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA
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4:30pm • Advanced Interrupt Architecture and Advanced CLINT - Anup Patel, Western Digital & John Hauser, Independent Researcher
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1:30pm • Keynote: Welcome & Opening Remarks - Calista Redmond, CEO, RISC-V International
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1:40pm • Keynote: Are the RISC-V Design Freedoms Leading to RISK in Verification Quality? - Larry Lapides, Vice President Sales, Imperas Software Ltd.
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1:55pm • Keynote: Bringing RISC-V to Life: Building our Software Ecosystem - Philipp Tomsich, Founder and Chief Technologist, VRULL GmbH
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2:10pm • Keynote: The Future of RISC-V has No Limits - Dr. Yunsup Lee, Co-Founder & Chief Technology Officer, SiFIve
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2:30pm • Keynote: The Showcase of RISC-V Wins!
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2:35pm • Keynote: Building Customized Solutions from Open-sources - Xiaoning Qi, Vice President, Alibaba Group
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2:45pm • Keynote: Diversity, Equity, and Inclusion in Open Hardware - Dr. Marjan Radi, Research Technologist Engineer, NVM Systems Architecture, Western Digital & Kim McMahon, Director of Visibility & Community Engagement, RISC-V International
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9:00am • Performance Monitoring in RISC-V using perf - Atish Patra, Western Digital
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9:30am • ACPI for RISC-V: Enabling Server Class Platforms - Sunil V L, Ventana Micro Systems
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10:30am • Efficient Issue Scheduling for Hardware Multithreaded RISC-V Pipeline - Dr. Shlomo Greenberg, Ben Gurion University of the Negev & Sami Shamoon College Engineering, Beer-Sheva, Israel
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11:00am • The Future of RISC-V Heterogeneous Embedded Virtualization Architectures - Sandro Pinto & José Martins, Universidade do Minho
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11:30am • Accelerating AI and non-AI Workloads with 1000+ Energy-Efficient RISC-V Cores on a Single Chip - Art Swift, Esperanto Technologies
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3:30pm • Sail Specification for RISC-V P-Extension - Bow-Yaw Wang, Academia Sinica, Taiwan & Jenq-Kuen Lee, National Tsing Hua University, Taiwan
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4:00pm • BoF: How RISC-V CPU Design Impacts Performance of Copy Function and Network Speed - Akira Tsukamoto, AIST
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1:30pm • Keynote: State of the Union - Krste Asanović, Professor, EECS Dept, U.C Berkeley / Chief Architect and Co-Founder, SiFive Inc.
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1:45pm • Keynote: Beefing Up the Datacenter Accelerators - Charlie Su, President and CTO, Andes Technology
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1:55pm • Keynote Panel: RISC-V Momentum at Data Center Scale - Balaji Baktha, Ventana (Moderator); Sumit Gupta, Google; Jing Yang, Alibaba; Roger Espasa, Semidynamics Technology Services; Bapi Vinnakota, Open Compute Project ODSA Project Lead
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2:25pm • Keynote: Microchip and the Expanding RISC-V Universe - Ted Speers, Technical Fellow, Microchip
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2:35pm • Keynote: The Showcase of RISC-V Wins!
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2:40pm • Keynote: Profiles and Platforms: RISC-V Convergence - Greg Favor, CTO, Ventana Micro Systems
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9:00am • RISC-V Enterprise Software Ecosystem Readiness - Kumar Sankaran, Ventana Micro Systems
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9:30am • Esperanto’s Custom RISC-V ISA Extensions for Energy-Efficient Machine Learning Applications - Jayesh Iyer, Esperanto Technologies
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10:30am • Quantitative Methods for Continuously Improving RISC-V Compilers - Philipp Tomsich, VRULL
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11:00am • Lightning Talk: Performance of TVM AutoScheduler for Andes Vector Processor - I-Wei Wu, Andes Technology
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11:15am • Lightning Talk: Bring Multicore RISC-V and Zephyr RTOS Together - Chun-Wei Shu, Andes Technology
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11:30am • A Requirements-based Test Suite for the C Standard Library: SuperGuard - Marcel Beemster, Solid Sands B.V.
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3:30pm • TEEP (Trusted Execution Environment Provisioning) and Software Updates for Internet of Things (SUIT) on RISC-V - Akira Tsukamoto, AIST
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4:00pm • Lightning Talk: Enabling RISC-V Software Ecosystem with VisionFive - an Affordable and Open Source RISC-V Single Board Development Platform with Support for Fedora - Chin Hu Ong, StarFive Technology
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4:15pm • Lightning Talk: First Volume Production RISC-V Silicon/SOC to Provide Complete Personal Computing Platform Solution Targeting Mid-range and Edge Computing - Johnson Sun, StarFive
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4:30pm • Storage Area Network Acceleration using RDMA / RoCE and RISC-V - Pu Wang, DatenLord
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9:00am • Lightning Talk: Functional Gap between RISC-V V and SPIR-V: a Study Case on the Graphics Domain - Abel Bernabeu, Esperanto Technologies
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9:15am • Lightning Talk: A Zero Trust Security Architecture For RISC-V SoC/ Platform - Suresh Sugumar, Technology Innovation Institute
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9:30am • Radiation Hardening and Fault-Tolerance Features of the NOEL-V RISC-V Processor - Jan Andersson, CAES Space System Division, Gaisler
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10:30am • Lightning Talk: Adding H Support to the NOEL-V Microprocessor - Stefano Ribes, De-RISC Project
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10:45am • Lightning Talk: A Secure RISC-V Based SoC for Autonomous UAVs Navigation - Davide Rossi, University of Bologna & Daniele Palossi, IDSIA USI-SUPSI Lugano
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11:00am • Unveiling the SweRV Core EH3 - Zvonimir Bandic, Western Digital
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11:30am • Profiles and Platforms - Philipp Tomsich, VRULL & Mark Himelstein, RISC-V International
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3:30pm • Systematically Securing the RISCV - Secure Foundation for Embedded Functionality - Marko Mitic, NVIDIA
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4:00pm • IOPMP Updates: The Protection of IOPMP - Paul Shan-Chyun Ku, Andes Technology
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4:30pm • Architecture Design for Security: Do’s and Don’ts - Gregory T. Sullivan, Dover Microsystems, Inc.
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1:30pm • Keynote: Road Ahead - Mark Himelstein, CTO, RISC-V International
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1:50pm • Keynote: Is Hardware/software Co-design for Applications Now a Reality with RISC-V? - Kevin McDermott, Vice President Marketing, Imperas Software Ltd
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2:00pm • Keynote: Awards Presentation - Kim McMahon, Director of Visibility & Community Engagement, RISC-V International & Mark Himelstein, CTO, RISC-V International
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2:15pm • Keynote: Scaling is Failing - Dr. Ron Black, CEO, Codasip
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2:30pm • Keynote: The Showcase of RISC-V Wins!
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2:40pm • Keynote: Where is RISC-V Going? - Calista Redmond, CEO, RISC-V International
